Low latency lock for multiprocessor computer system

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Reexamination Certificate

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Details

C711S147000, C711S151000, C711S153000, C711S163000, C711S141000, C711S146000

Reexamination Certificate

active

06986005

ABSTRACT:
A multinodal multiprocessor computer system and method is provided in which a first processor can acquire exclusive access to a first memory location in a shared memory, and at the same time a second processor can access to a second memory location of the shared memory that is located in the same node or in any other node of the computer system. Memory controllers in each node of the computer system control access to the shared memory. A switch coupled to each of the memory controllers maintains a lock register, which is shadowed by each of the memory controllers, for controlling access to the first memory location.

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