Low power cache operation through the use of partial tag...

Details Low power cache operation through the use of partial tag... Low power cache operation through the use of partial tag...

1999-07-27

2002-09-10

Elmore, Reba I. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000

Reexamination Certificate

active

06449694

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of cache memory design, and more specifically, to a low power cache operation.
2. Background Information
A cache memory is a storage system incorporated either inside a central processor or between a processor and a main system memory. A cache memory stores instructions or data and it is able to supply this information to the processor faster than the main memory can. When a memory read operation is requested by the processor, the cache memory is checked to determine whether or not the data is present in the cache memory. If the cache contains the referenced data, the cache provides the data to the processor. Otherwise, the data is accessed from the main memory.
A cache memory uses a data array to store data and a tag array to store the tag addresses corresponding to the data. A main memory address consists of a tag field and an index field. The index field is used to index a specific tag address stored in the cache tag array. When a cache memory access is performed, the tag address stored in the cache tag array is read and it is then compared to the tag field of the main memory address. If the two tag addresses match, a cache “hit” has occurred and the corresponding data is read out to the processor. If the two tag addresses do not match, a cache “miss” has occurred and the data must be retrieved from the main memory.
Often, it is desirable to verify the integrity of the tag stored in the cache memory. Checking the validity and the parity of the tag address may be performed in order to assure that the tag is not corrupted or altered. In prior art methods, while the tag is compared, the valid bit and the parity bit of the tag address are verified. For example,
FIG. 1
illustrates a prior art cache memory read operation. After receiving a memory address at box
100
and decoding a tag address from the cache tag array at box
110
, the tag address, the parity bit, and the valid bit are read at box
120
. At box
130
, the tag, the parity bit, and the valid bit are then compared. If a “hit” has occurred, and the tag is determined to be valid, and the parity bit of the tag address matched the parity bit of the tag field of the main memory, then at box
140
, the data is read from the cache memory. Otherwise, if either the valid bit or the parity bit does not match, or if a cache “miss” has occurred, then, at box
150
, the cache memory operation is canceled.
It should be noted that for a set associative cache, the tag address, the parity, and the valid bit are read at box
120
for each way of the cache array. Similarly, at box
130
, the tag, parity, and valid bits are compared for each way of the cache array. As such, if all comparisons for all ways result in a “miss”, the data has to be accessed from the main memory. Otherwise, the way associated with the tag having a match is the way selected for conveying data bytes to the output of the cache.
The operation illustrated in
FIG. 1
is, however, not suitable for a low power cache memory. Because the tag address is entirely read and compared while a validity or parity test is performed, a lot of power may be consumed before detecting an error.
Thus, it would be advantageous to provide a cache memory and a method for performing low power cache operations that minimize tag read and compare operations.
SUMMARY OF THE INVENTION
A method for conserving power during a cache memory operation is disclosed. A memory address comprising a tag field is received. A tag address within the cache memory is accessed. The tag address bits are selected in a plurality of tag subsets. A first tag subset of the plurality of tag subsets is compared with a respective first subset of the tag field of the memory address bits. A first compare signal indicative of the result of the first comparison is outputted. The cache memory operation is interrupted if the first compare signal indicates the first tag subset does not match the respective first subset of the tag field of the memory address.
Additional features and benefits of the present invention will become apparent from the detailed description, figures, and claims set forth below.


REFERENCES:
patent: 4483003 (1984-11-01), Beal
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patent: 5550774 (1996-08-01), Brauer et al.
patent: 5553276 (1996-09-01), Dean
patent: 5555529 (1996-09-01), Hose et al.
patent: 5920888 (1999-07-01), Shirotori et al.
patent: 6122696 (2000-09-01), Brown et al.
patent: 6131140 (2000-10-01), Rodgers et al.

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