Low latency buffer control system and method

Details Low latency buffer control system and method Low latency buffer control system and method

2005-01-11

2005-01-11

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C713S324000, C710S039000, C710S052000, C710S112000, C710S118000, C710S310000, C365S189050, C365S194000, C365S226000, C365S227000, C365S230010, C365S230010

Reexamination Certificate

active

06842831

ABSTRACT:
A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffer coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the “enable buffer” delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.

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