Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-05-10
2005-05-10
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S147000, C711S151000, C700S005000, C709S215000
Reexamination Certificate
active
06892290
ABSTRACT:
Early race conditions caused by multiple computer system entities issuing memory reference operations for a given memory block are resolved by creating linked lists identifying the entities. The lists are preferably formed by storing information and state in miss address file (MAF) entries maintained by the entities. The MAF entries cooperate to form one or more read chains each of which links the entities requesting read access to a particular version of the given memory block. The MAF entries also cooperate to form a single write chain that links the entities requesting write access to the given memory block. When the desired memory block becomes available, the information and state stored at the MAF entries is then utilized by each entity in satisfying its obligations as part of the read and write chains, thereby ensuring that each entity receives the version of the given memory block that it desires.
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Hewlett--Packard Development Company, L.P.
Moazzami Nasser
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