Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-12-30
2008-11-25
Nguyen, Hiep T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
Reexamination Certificate
active
07457932
ABSTRACT:
A method is disclosed. The method includes scheduling a load operation at least twice the size of a maximum access supported by a memory device, dividing the load operation into a plurality of separate load operation segments having a size equivalent to the maximum access supported by the memory device, and performing each of the plurality of load operation segments. A further method is disclosed where a temporary register is used to minimize the number of memory accesses to support unaligned accesses.
REFERENCES:
patent: 5896505 (1999-04-01), Shimazaki
patent: 2004/0148490 (2004-07-01), Anderson et al.
patent: 2004/0212623 (2004-10-01), Yi et al.
Fetterman Michael
Hammarlund Per
Hily Sebastien
Hinton Glenn
Jourdan Stephan
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Hiep T
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