Linear combiner weight memory

Details Linear combiner weight memory Linear combiner weight memory

2007-04-17

2010-12-07

Choe, Yong (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C342S194000, C370S206000

Reexamination Certificate

active

07849283

ABSTRACT:
A linear combiner weight memory. Various embodiments of the weight memory provide a weight bank and control logic. The weight bank is operable to couple with a data stream and may include four registers. The first register is operable to store a first in-phase weight value. The second register is operable to store a second in-phase weight value and be written with the second in-phase weight value while the first in-phase weight value is read from the first register. The third register is operable to store a first quadrature weight value. The fourth register is operable to store a second quadrature weight value and be written with the second quadrature weight value while the first quadrature weight value is read from the third register.

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