Latency reduction using negative clock edge and read flags

Details Latency reduction using negative clock edge and read flags Latency reduction using negative clock edge and read flags

2006-05-30

2006-05-30

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S115000, C711S005000, C713S400000, C710S105000, C710S112000

Reexamination Certificate

active

07055012

ABSTRACT:
A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because different memory devices may have different CAS latencies, a system CAS latency is selected wherein the system CAS latency is the fastest common CAS latency of each of the plurality of memory devices. After a read request is delivered to a memory device, the memory controller initiates a transmission flag to the memory device at a time equal to the system CAS latency, indicating that it is safe to transmit the requested data from the memory device to the memory controller. The transmission flags may be used in conjunction with mode registers such that one or both of the transmission flag and the data may be received by or delivered by a corresponding memory device.

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