Two address map for transactions between an X-bit processor...
Two level address translation and memory registration system and
Two-part memory address generator
Unaligned memory operands
Universal PTE backlinks for page table accesses
Updating and invalidating store data and removing stale...
User interface system for a multi-protocol storage appliance
Using an IOMMU to create memory archetypes
Using current recovery mechanisms to implement dynamic...
Using short references to access program elements in a large...
Using vector processors to accelerate cache lookups
Variable format memory access device
Vector indexed memory unit and method
Vector indexed memory unit and method
Vector register addressing
Vector transfer system for packing dis-contiguous vector...
Very high speed page operations in indirect accessed memory...
Video memory arrangement
Virtual address bypassing using local page mask
Virtual address cache and method for sharing data using a...