Vector register addressing

Details Vector register addressing Vector register addressing

1998-08-28

2001-12-18

Niebling, John F. (Department: 2812)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S100000

Reexamination Certificate

active

06332186

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of data processing. More particularly, this invention relates to data processing systems having vector data processing registers.
2. Description of the Prior Art
A data processing instruction typically includes within it an opcode portion and one or more register specifying fields. In some systems a register may be treated as a vector register or a scalar register. A vector register specifies a sequence of registers each storing its own data value which is separately operated upon as the data processing instruction repeats its operation upon each data value in the sequence. Conversely a scalar register is a single register storing a single value that operates independently of other registers.
Data processing instructions using vector registers have a number of advantages over purely scalar operations. The instruction bandwidth required may be reduced since only a single data processing instruction is required to specify a plurality of similar data processing operations to be performed (common in DSP functions such as FIR filters). In the case of a single-issue machine (i.e. one instruction is fetched and decoded each cycle), which is desirable because of its simplicity, higher performance can be achieved with multiple functional units that execute in parallel on different vector instructions.
FIGS. 16 and 17
of the accompanying drawings respectively illustrate a Cray 1 processor register bank and a Digital Equipment Corporation MultiTitan processor register bank. Both of these prior art processors provide vector and scalar registers.
In the case of the Cray 1, separate vector and scalar register barks
10
,
12
are provided. A 16-bit instruction provides individual opcodes that correspond to different combinations of the registers specified in the instructions being treated as vectors or scalars. 3-bit register specifying fields R1, R2, R3 allows 8 scalar registers and 8 vector registers to be addressed. In practice, each vector register comprises a stack of registers that can each store a different data value and be accessed in turn in dependence upon a vector length value stored within a length register
16
and mask bits stored within a mask register
18
.
The Cray 1 processor also utilizes a scatter gather mechanism that allows loads and stores to non-contiguous addresses within the memory such that interleaved matrix and/or complex values stored within the main memory can be loaded into the appropriate registers for later manipulation.
Whilst the Cray 1 architecture provides a great deal of flexibility in the operations that can be supported is requires a disadvantageously large overhead in term of cost and complexity.
The MultiTitan processor provides a single register bank
20
in which each register may operate as a scalar or as part of a vector register. The MultiTitan processor uses a 32-bit instruction to specify its data processing operations. The instructions include fields VS
2
, VS
3
that specify whether the registers are vectors or scalars and the length of the vectors (Len). The provision of the vector length within the instruction itself makes it difficult to make global changes to the vector length without having to resort to self-modifying code. If the data upon which the processor is operating is interleaved matrix and/or complex data, then individual load and store operations have to be performed to load and store each data item to be manipulated by the vector instruction. This is disadvantageously inefficient.
SUMMARY OF THE INVENTION
It is an object of the present invention to address at least some of the limitations of the above-described systems.
Viewed from one aspect the present invention provides apparatus for data processing, said apparatus comprising:
a register bank having a plurality of registers for holding data values to be manipulated, each of said registers having a register address;
a memory accessing circuit responsive to at least one block memory access instruction for performing memory accesses between a plurality of contiguously addressed memory locations within a memory and a plurality of contiguously addressed registers within said register bank; and
an instruction decoder responsive to at least one vector processing instruction for sequentially executing a data processing operation a plurality of times upon operands stored within a predetermined sequence of said registers; wherein
between each execution of said data processing operation, said instruction decoder is responsive to a stride value to increment a register address of a register storing an operand used in said data processing operation by an amount specified by said stride value.
The invention allows the use of simple to implement contiguous block memory access instructions without the cost and complexity of a scatter gather mechanism. The increment (variable between vectors) that is applied to the register address upon each iteration permits the system to step through non-adjacent data value thereby selecting the appropriate matrix, real or imaginary value to be processed. In practice it has been found that the restriction to a fixed increment between register addresses within execution of a vector instruction is not a significant constraint since many important real-life tasks match this behaviour. In summary, the system is able to exploit efficient block memory access instructions to a memory in which the data is arranged in a flat form whilst preserving the vector processing ability to specify a sequence of operations with a single instruction.
Whilst it is possible to provide each register specified in a vector processing operation with its own stride value, in preferred embodiments said stride value applies to all registers operating as vector registers when executing said vector processing instruction.
This feature simplifies the implementation and has in practice been found not to cause a significant constraint.
In a similar manner, it is possible for the stride value to be specified within the vector instruction itself. However, in preferred embodiments of the invention said stride value is set independently of said vector processing instruction.
This feature saves bit-space within the vector instruction without in practice causing a significant constraint upon the processing to be performed. It has been found that in practice the stride value usually remains constant for a long period and so the bit-space saved within the instructions more than compensates for the occasional need to execute a specific instruction to change the stride value.
It has been found particularly efficient to use embodiments in which said stride value is stored within a control register, said stride value specifying said amount of said register address increment for all vector processing instructions executed.
The incrementing of the register address between vector operations can be conveniently achieved by providing embodiments in which said instruction decoder includes a register address adder that increments said register address by summing a current register address input to a first adder input and said amount input to a second adder input.
Such embodiments represent a lower overhead in terms of cost and complexity in providing a system able to use block memory access instructions and perform data processing operations using a vector instruction even though the operands are not contiguously arranged within the memory in the order in which they are to be used.
Whilst it is possible the stride value to directly represent the amount to be incremented, in preferred embodiments of the invention said stride value is an encoded representation of said amount.
In practice it is found that the increments that are commonly provided are a subset of all possible increment values and so it is more efficient to have the stride value encode the amount rather than wasting bit-space in having the stride value directly represent the amount.
An increased degree of sophistication is provided in embodiments in whi

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