Two level address translation and memory registration system and

Details Two level address translation and memory registration system and Two level address translation and memory registration system and

1998-12-30

2000-12-19

Lane, Jack A.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

G06F 1210

Patent

active

06163834&

ABSTRACT:
A two-level memory region registration and address translation method includes a memory handle table and a translation and protection table (TPT). Each memory region registered is associated with a unique memory handle index which accesses one entry of the memory handle table. The accessed entry in the memory handle table stores a memory handle that is combined with virtual addresses in the registered memory region to access TPT entries storing translation data for the virtual addresses in the registered memory region.

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