Two address map for transactions between an X-bit processor...

Details Two address map for transactions between an X-bit processor... Two address map for transactions between an X-bit processor...

2008-04-15

2008-04-15

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S201000, C711S209000

Reexamination Certificate

active

07360055

ABSTRACT:
Presented herein are systems and methods for two address map for transactions between an X-bit processor and a Y-bit wide memory. A processor subsystem comprises a first address space, a second address space, and a bridge. The first address space stores data words of a first length. The second address space stores data words of a second length. The bridge performs one transaction after receiving a transaction with an address corresponding to the first address space and performs two transactions after receiving a transaction with the address corresponding to the second address space.

REFERENCES:
patent: 5761443 (1998-06-01), Kranich
patent: 6694392 (2004-02-01), Haren
patent: 6750781 (2004-06-01), Kim
patent: 7000045 (2006-02-01), Holm et al.

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