Using vector processors to accelerate cache lookups

Details Using vector processors to accelerate cache lookups Using vector processors to accelerate cache lookups

2005-06-15

2008-11-04

Ellis, Kevin (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S118000, C711S202000, C711S205000

Reexamination Certificate

active

07447868

ABSTRACT:
Typical embodiments of the present invention maintain the cache metadata in arrays, and use vector instructions to process the array elements in parallel. The cache metadata comprises virtual tags corresponding to main memory addresses and physical addresses corresponding to cache memory addresses. The virtual tags and physical addresses may be interleaved in a single array in the cache memory. Alternately, virtual tags and physical addresses may be maintained in corresponding separate arrays. A roving pointer may be used to identify the next block to be ejected from the cache memory.

REFERENCES:
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patent: 5325507 (1994-06-01), Freitas et al.
patent: 5379393 (1995-01-01), Yang
patent: 6496902 (2002-12-01), Faanes et al.
patent: 0 352 633 (1990-01-01), None

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