Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2009-03-27
2011-11-15
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C710S100000, C711SE12008
Reexamination Certificate
active
08060722
ABSTRACT:
Some embodiments of the present invention include an execution unit of a processor and a memory management unit interposed between the execution unit and an interface to memory suitable for storage of both guest page tables maintained by a guest operating system and shadow page tables maintained generally in correspondence with the guest page tables by virtualization software. The memory management unit is configured to walk in-memory data structures that encode the shadow page tables, to access entries of the shadow page tables and, based thereon or on a cached representation of page mappings therein, to perform virtual-to-physical address translations relative to memory targets of instructions executed by the execution unit. The memory management unit is responsive to a shadowed write indication coded in association with either an entry of the shadow page tables or a cached representation of a page mapping therein used to perform the virtual-to-physical address translation for a write-type one of the instructions that targets an entry of one of the guest page tables. The memory management unit is configured to complete the memory access of the write-type instruction that targets the guest page table entry and to store in a buffer, information sufficient to allow the virtualization software to later update an entry of the shadow page tables in correspondence therewith.
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Adams Keith
Rihan Sahil
Bataille Pierre-Michel
VMware, Inc.
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