High speed translation lookaside buffer employing content addres

Details High speed translation lookaside buffer employing content addres High speed translation lookaside buffer employing content addres

1997-11-05

2000-01-04

Cabeca, John W.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711206, 711207, G06F 1210

Patent

active

060121319

ABSTRACT:
A translation lookaside buffer (TLB) for use of a microprocessor, using a content address memory (CAM), includes a block for generating a control clock for precharging a clock and an enable clock for driving data; a CAM block for comparing a linear address with stored data and generating hit signals representing whether or not its comparison result is a coincidence therebetween; a block for decoding the linear address applied from the outside, the linear address being for a distinction of respective entries; a hit signal generating block for outputting selection signals indicating where the hit signals inputted from the CAM block are generated; a block for storing a physical address; a block for selecting one out of the physical addresses outputted from each area of the storing block in response to the selection signal provided from the hit signal generating block; and a block for sensing a signal applied from the selection block.

REFERENCES:
patent: 5440707 (1995-08-01), Hayes et al.
patent: 5606683 (1997-02-01), Riordan
patent: 5740410 (1998-04-01), McDermott
patent: 5805490 (1998-09-01), Machida
patent: 5835963 (1998-11-01), Yoshioka et al.
patent: 5893931 (1999-04-01), Peng et al.
patent: 5907867 (1999-05-01), Shinbo et al.

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