High performance memory device-state aware chipset prefetcher

Details High performance memory device-state aware chipset prefetcher High performance memory device-state aware chipset prefetcher

2006-01-03

2006-01-03

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Generating prefetch, look-ahead, jump, or predictive address

C711S204000, C711S108000, C711S137000, C712S237000, C712S238000, C712S239000

Reexamination Certificate

active

06983356

ABSTRACT:
A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the memory bandwidth utilization (MBU) rate is above a MBU threshold level and the prefetch buffer hit rate (PBHR) is above a PBHR threshold level. Prefetches are inserted conservatively if the memory bandwidth utilization (MBU) rate is above the MBU threshold level and the prefetch buffer hit rate (PBHR) is below the PBHR threshold level.

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Lin, et al., Reducing DRAM Latencies with an Integrated Memory Hierarchy Design, IEEE, 2001, pp. 301-312.

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