High speed four-to-two carry save adder

Details High speed four-to-two carry save adder High speed four-to-two carry save adder

1998-05-06

2001-07-24

Ellis, Kevin L. (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

Reexamination Certificate

active

06266757

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to microprocessors, and more specifically to performing high speed add operations in an address generation unit.
BACKGROUND OF THE INVENTION
Instruction execution circuits within microprocessors include address generation units that decode addresses encoded within microprocessor instructions. The decoded addresses specify the locations in memory containing instructions to be executed or data to be accessed. Many present microprocessors feature advanced architectures that allow parallel processing and pipelined instruction execution. Such architectures allow microprocessors to decode, dispatch, and complete execution of (retire) multiple instructions in a single clock cycle. For example, in the Pentium® Pro microprocessor produced by Intel Corporation, a three-way superscalar, pipelined architecture allows for retirement of as many as three instructions per clock cycle. “Pentium” and “Pentium Pro” are registered trademarks of Intel Corporation of Santa Clara, Calif.
Parallel processing techniques and the use of fast temporary memory, such as caches for instructions and data, require extensive decoding of address information to generate proper memory locations from which to fetch instructions and data. For example, code that contains multiple levels of branches and procedure calls that allow for out-of-order instruction execution produce often complex address relationships that must be properly resolved for proper instruction execution. The use of traditional fixed addresses in such processing environments is often insufficient to execute modern complex code. Accordingly, most present microprocessors use dynamic address schemes in which addresses are provided through address components that are derived and combined to produce linear address values.
The generation of dynamic addresses requires extensive logic circuitry to decode addresses encoded within the processor instructions. Such circuitry includes adder circuits within the instruction execution units that calculate memory locations based on the encoded address information. As the speed of microprocessors increases, the speed of these adder circuits must also increase so that gate delays are minimized to ensure that addresses are generated fast enough to maintain high instruction cycle rates.
Present adder circuits typically use static combinatorial logic and multiplexer circuits to perform addition operations on address information. With present microprocessor speeds exceeding 200 MHz, and approaching 1000 MHz, these static logic output circuits introduce gate delays that often prevent the execution of multiple instructions during single clock cycles.
SUMMARY OF THE INVENTION
A circuit is disclosed for performing four input to two output carry save addition operations in an address generation unit of a microprocessor. An adder circuit receives two or more numbers to be added together. The adder circuit includes a number of logic circuits that generate intermediate outputs. The intermediate outputs are input to a domino multiplexer. The domino multiplexer includes a multiplexer gate and an exclusive-or gate connected in parallel. The domino multiplexer circuit outputs a sum value and a carry value for the input numbers. A clock signal drives the multiplexer gate and the exclusive-or gate in the domino multiplexer circuit. This clock signal synchronizes the input of the numbers to be added together and the addition operation in the domino multiplexer circuit.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.


REFERENCES:
patent: 4023027 (1977-05-01), Strathman et al.
patent: 5625582 (1997-04-01), Timko
patent: 5818747 (1998-10-01), Wong
patent: 5993051 (1999-11-01), Jiang et al.
Yee et al., “Clock-Delayed Domino For Adder and Combinational Logic Design”, 1996, p. 332-337, IEEE.

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