Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
Patent
1997-08-27
1999-11-09
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Incrementing, decrementing, or shifting circuitry
711200, 711220, 711211, G06F 1200
Patent
active
059833335
ABSTRACT:
In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative of one greater than an ending address, a second input that is a beginning address, and a select input that is the sign of a displacement for stepping through addresses in a circular buffer. The first selector is adapted to select one of its inputs as an output. A first adder combines an address pointer and displacement to produce a first potential next address pointer. A second adder combines the address pointer, the displacement, and a length modified by the sign of the displacement to produce a second potential next address pointer. A sign detector performs a comparison to determine whether a sum of the address pointer, displacement and a negative representation of the first selector output is greater than or equal to zero, or less than zero, and provides an output. A second selector selects one of the first potential next address pointer or the second potential next address pointer as the next address pointer based on the comparator output.
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Kolagotla Ravi Kumar
Prasad Mohit Kishore
Chan Eddie P.
Lucent Technologies - Inc.
McLean Kimberly
Smith David L.
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