Hashing and serial decoding techniques

Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry

Reexamination Certificate

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C711S216000, C711S217000, C711S218000

Reexamination Certificate

active

07421563

ABSTRACT:
A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.

REFERENCES:
patent: 4667313 (1987-05-01), Pinkham et al.
patent: 5452255 (1995-09-01), Mine et al.
patent: 6639867 (2003-10-01), Shim
patent: 6785278 (2004-08-01), Calvignac et al.
patent: 6804768 (2004-10-01), Moyer
patent: 6907439 (2005-06-01), Wicker

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