Hardware demapping of TLBs shared by multiple threads

Details Hardware demapping of TLBs shared by multiple threads Hardware demapping of TLBs shared by multiple threads

2008-06-03

2008-06-03

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S202000, C711S203000, C711S204000, C711S205000, C711S206000

Reexamination Certificate

active

07383415

ABSTRACT:
In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one update to the TLB is pending for at least one of a plurality of strands. Each strand comprises hardware to support a different thread of a plurality of concurrently activateable threads in the processor. The strands share the TLB, and the control unit is configured to delay a demap operation issued from one of the estrands responsive to the pending update, if any.

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Office Action from U.S. Appl. No. 11/222,614, mailed Aug. 8, 2007.
Office Action from U.S. Appl. No. 11/222,614, mailed Oct. 31, 2007.

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