Processor having systolic array pipeline for processing data...

Processor having systolic array pipeline for processing data...

Processor interconnection

Processor interface for a distributed memory addressing system

Processor interrupt filtering

Processor local bus bridge for an embedded processor block...

Processor local bus posted DMA FlyBy burst transfers

Processor receiving response request corresponding to access clo

Processor reset generated via memory access interrupt

Processor selection for an interrupt based on willingness to...

Processor state aware interrupts from peripherals

Processor surrogate for use in multiprocessor systems and...

Processor that indicates system bus ownership in an upgradable m

Processor that maintains virtual interrupt state and injects...

Processor transparent on-the-fly instruction stream...

Processor virtualization mechanism via an enhanced...

Processor with coherent bus controller at perpendicularly...

Processor with input data block discard mechanism for use in...

Processor with internal register for peripheral status

Processor with internal register for peripheral status