Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2011-08-23
2011-08-23
Spittle, Matthew (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S110000, C710S305000, C710S307000, C710S317000
Reexamination Certificate
active
08006021
ABSTRACT:
A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.
REFERENCES:
patent: 4346377 (1982-08-01), Green
patent: 5590304 (1996-12-01), Adkisson
patent: 6101565 (2000-08-01), Nishtala et al.
patent: 6208667 (2001-03-01), Caldara et al.
patent: 6275890 (2001-08-01), Lee et al.
patent: 6502173 (2002-12-01), Aleksic et al.
patent: 6546451 (2003-04-01), Venkataraman et al.
patent: 6640275 (2003-10-01), Kincaid
patent: 6760802 (2004-07-01), Jahnke et al.
patent: 6940311 (2005-09-01), Saitoh
patent: 6985988 (2006-01-01), Nsame
patent: 7076595 (2006-07-01), Dao et al.
patent: 7174403 (2007-02-01), Ganasan
patent: 7185121 (2007-02-01), Fitzsimmons et al.
patent: 7219177 (2007-05-01), Chang et al.
patent: 7234011 (2007-06-01), Chae
patent: 7266632 (2007-09-01), Dao et al.
patent: 7275120 (2007-09-01), Ou et al.
patent: 7277976 (2007-10-01), Hoshi et al.
patent: 7373450 (2008-05-01), Kamegawa
patent: 7426600 (2008-09-01), Takaba
patent: 7461187 (2008-12-01), Morishita et al.
patent: 7526595 (2009-04-01), Drerup et al.
patent: 7554355 (2009-06-01), Chang et al.
patent: 2003/0191891 (2003-10-01), Tanaka et al.
patent: 2004/0123036 (2004-06-01), Hammitt et al.
patent: 2005/0273544 (2005-12-01), Fitzsimmons et al.
patent: 2007/0283077 (2007-12-01), Klein et al.
Drake et al. Panic! Unix System Crash Dump Analysis. Chapter 15. Section “Basic CPU Structure” (all CPUs are similar). 1995.
Altera Corporation. Avalon Memory-Mapped Design Optimizations. Embedded Design Handbook. Jun. 2008.
Taylor et al. 28nm Generation Programmable Families. Xilinx. Aug. 8, 2010.
Bafumba-Lokilo et al. Generic Crossbar Network on Chip for FPGA MPSoCs. IEEE. 2008.
Hauck et al. Mesh Routing Topologies for Multi-FPGA Systems. IEEE Transactions on VLSI Systems. vol. 6. No. 3. pp. 400-408. Sep. 1998.
U.S. Appl. No. 12/043,097, filed Mar. 5, 2008, Ansari, Ahmad R., et al., entitled “A Processor Block Asic Core for Embedding in an Integrated Circuit”, Xilinx, Inc. 2100 Logic Drive, San Jose, California 95124.
IBM Doc. No. SA-14-2538-04, “128-bit Processor Local Bus Architecture Specifications”, Ver. 4.6, Jul. 2004, 184 pages.
UG200 (v1.0), “Embedded Processor Block in Virtex-5 FPGAs”, Jan. 15, 2008, 323 pages, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
UG200 (v1.1), “Embedded Processor Block in Virtex-5 FPGAs”, Mar. 31, 2008, 327 pages, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
Ansari Ahmad R.
Appelbaum Jeffery H.
Li Kam-Wing
King John J.
Spittle Matthew
Webostad W. Eric
Xilinx , Inc.
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