Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-06-27
2006-06-27
Myers, Paul R. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S038000, C712S010000, C712S011000, C712S019000, C709S238000
Reexamination Certificate
active
07069372
ABSTRACT:
A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of programmable functional units and register files arranged sequentially as stages, for processing packet contexts (which contain the packet's destination address) to perform operations, under programmatic control, to determine the destination port of the router for the packet. A single stage of the systolic array may contain a register file and one or more functional units such as adders, shifters, logical units, etc., for performing, in one example, very long instruction word (vliw) operations. The processor may also include a forwarding table memory, on-chip, for storing routing information, and a cross bar selectively connecting the stages of the systolic array with the forwarding table memory.
REFERENCES:
patent: 5524258 (1996-06-01), Corby et al.
patent: 5734649 (1998-03-01), Carvey et al.
patent: 5781772 (1998-07-01), Wilkinson, III et al.
patent: 5905725 (1999-05-01), Sindhu et al.
patent: 5909440 (1999-06-01), Ferguson et al.
patent: 5930256 (1999-07-01), Greene et al.
patent: 6011795 (2000-01-01), Varghese et al.
patent: 6018524 (2000-01-01), Turner et al.
patent: 6078963 (2000-06-01), Civanlar et al.
patent: 6091725 (2000-07-01), Cheriton et al.
patent: 6101192 (2000-08-01), Wakeland
patent: 6430181 (2002-08-01), Tuckey
patent: 6675187 (2004-01-01), Greenberger
patent: 6687781 (2004-02-01), Wynne et al.
patent: 6795886 (2004-09-01), Nguyen
patent: 6804815 (2004-10-01), Kerr et al.
“Xelerated Packet Devices”, MicroDesign Resources Presentation, Network Processor Forum, pp. 1-11, (Jun. 14, 2001).
Cataldo, Anthony, “Net Processor Startup Takes Pipelined Path to 40 Gbits/s”, EE Times, http://www.eetimes.com/story/OEG20010702S0061, (Jul. 2, 2001).
Kung, H. T. et al. “Algorithms for VLSI Processor Arrays”, In Introduction to VLSI Systems, Mead C. et al., Eds. Addison-Wesley, Reading, Mass., pp. 271-292 (1980).
Partridge, Craig et al., “A 50-Gb/s Router”, IEEE/ACM Transactions on Networking, vol. 6, No. 3, (Jun. 1998).
Degermark, Mikael et al., “Small Forwarding Tables for Fast Routing Lookups”, Lulea University of Technology, (date unknown).
Lampson, B. et al., “IP Lookups Using Multiway and Multicolumn Search”, (Aug. 1, 1997).
Gupta, Pankaj et al., “Routing Lookups in Hardware at Memory Access Speeds”, Stanford University, IEEE Infocom, http://www.stanford.edu, (Apr. 1998).
McAuley, Anthony J. et al., “Fast Routing Table Lookup Using CAMs”, http://www.citeseer.nj.nec.com, Infocom '93, (Mar.-Apr. 1993).
Lindberg, Klaus, Multi-gigabit Routers, http://www.tml.hut.fi/Opinnot/Tik-110.551/1998/papers, (May 3, 1998).
Belenkiy, Andrey, “Deterministic IP Table Lookup at Wire Speed”, New Jersey Institute of Technology, http://www.isoc.org/inet99/proceedings/4j/4j—2.htm, (printed Jul. 24, 2000).
Chiueh, Tzi-cker et al., “High-Performance IP Routing Table Lookup Using CPU Caching”, State University of New York, Proceedings of IEEE Infocom, http://citeseer.nj.nec.com/216222.html, (1999).
Waldvogel, Marcel et al., “Scalable High Speed IP Routing Lookups”, Computer Engineering and Networks Laboratory, http://citeseer.nj.nec.com/did/12751, (1997).
“What's inside a router?” http://www-net.cs.umass.edu/kurose
etwork/inside/inside.htm, retrieved Aug. 29, 2005, p. 1-11.
Leung, Jr. Arthur
Li Anthony J.
Lynch William L.
Mehrotra Sharad
Cisco Technology, inc.
Myers Paul R.
Phan Raymond N
Schwegman Lundberg Woessner & Kluth P.A.
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