Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt inhibiting or masking
Reexamination Certificate
2006-08-29
2006-08-29
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt inhibiting or masking
C710S266000, C710S268000
Reexamination Certificate
active
07099977
ABSTRACT:
A method for processing an interrupt message in a system having a plurality of processors arranged into at least two partitions. The interrupt message is decoded to identify an interrupt source. If the interrupt source is not in an interrupt set, the interrupt is dropped. If the interrupt source is in a local partition, the interrupt is delivered. If the interrupt source is in the interrupt set and not in the local partition, the interrupt is processed in accordance with at least one of a target enable register and a vector enable register.
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patent: 7000051 (2006-02-01), Armstrong et al.
patent: 2002/0152344 (2002-10-01), Holm et al.
patent: 2004/0019723 (2004-01-01), Ostrovsky et al.
patent: 2004/0210705 (2004-10-01), Armstrong et al.
Chong Huai-Ter Victor
Gostin Gary Belgrave
Warner Craig W.
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