Processor interface for a distributed memory addressing system

Details Processor interface for a distributed memory addressing system Processor interface for a distributed memory addressing system

1996-10-04

2000-03-21

Thai, Xuan M.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710131, 710132, 711147, G06F 1300

Patent

active

060413794

ABSTRACT:
A processor interface for interfacing a CPU with a global memory and with other CPUs uses a node control bus for transmitting task and addressing information, and a fixed-speed, time-multiplexed direct connection to each memory block for data transmission. This arrangement provides a totally non-blocking interface between a CPU and a global SRAM memory.

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