Microprocessor with external memory interface optimized by...

Minimal frame buffer manager allowing simultaneous...

Moving, resizing, and memory management for...

Moving, resizing, and memory management for...

Multi-channel fractional clock data transfer

Multi-function peripheral device for preventing the execution of

Multi-port internally cached DRAM system utilizing independent s

Multi-queue FIFO memory devices that support flow-through of...

Multi-queue quality of service communication device

Multi-rate optimized connection between industrial control...

Multi-reader multi-writer circular buffer memory

Multifunctional I/O organizer unit for multiprocessor...

Multiple channel data communication buffer with separate single

Multiple insertion point queue to order and select elements to b

Multiple transparent access to in put peripherals

Multiport data buffer having multi level caching wherein each da

Multirate circular buffer and method of operating the same

Network distributed site cache RAM claimed as up/down stream req

Network for increasing transmit link layer core speed

Network interface having adaptive transmit start point for each