Multi-port internally cached DRAM system utilizing independent s

Details Multi-port internally cached DRAM system utilizing independent s Multi-port internally cached DRAM system utilizing independent s

1998-07-06

2000-08-22

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710107, 710131, 711105, 711119, G06F 1300, G06F 1336

Patent

active

061087254

ABSTRACT:
A novel low cost/high performance multi-port internally cached dynamic random access memory architecture called `AMPIC DRAM`, and consequentially a unique system architecture which eliminates current serious system bandwidth limitations, providing a means to transfer blocks of data internal to the chip, orders of magnitude faster than the traditional approach, and with the chip also interconnecting significantly higher numbers of resources with substantially enhanced performance and at notably lower cost. Through use of a system configuration based on this novel architecture and working equally efficiently for both main memory functions and as graphics memory, thus providing a truly low cost, high performance unified memory architecture.

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patent: 5457654 (1995-10-01), McLaury
patent: 5490112 (1996-02-01), Hush et al.
patent: 5550961 (1996-08-01), Chimoto
patent: 5581773 (1996-12-01), Glover

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