Multirate circular buffer and method of operating the same

Details Multirate circular buffer and method of operating the same Multirate circular buffer and method of operating the same

2002-02-01

2004-10-19

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S053000, C710S056000

Reexamination Certificate

active

06807589

ABSTRACT:

The present invention relates to circular buffers and methods of operating the same especially for applications in telecommunications systems and methods and in computers more especially those in which multirate data has to be received and stored temporarily. For example, such applications may include digital signal processing (DSP), channel equalization, channel coding, interleaving, compression, encryption, speech encoding and decoding, etc.
BACKGROUND OF THE INVENTION
There are many applications in telecommunications in which data is received at different data rates, e.g. when transmitting or receiving uncompressed or compressed speech messages, video, data, fax. The “multi-media revolution” requires the transmission and reception of a wide variety of data types, formats and rates. Such data is often processed by algorithms which require temporary storage or buffering of the data while this processing is carried out. Once processed all record of the data is deleted from memory or overwritten by the next data to be processed.
One way of buffering such data is in a circular buffer. Hardware solutions for such buffers have achieved a high level of sophistication. These solutions are often based on modulo arithmetic for the calculation of addresses in memory because such arithmetic can be carried out very efficiently in a digital system. However, when dealing with data which may arrive at different data rates there exists a problem as how to optimize the size of memories used to buffer the data. Third generation mobile telecommunications systems such as UMTS require multirate data processing, the data rate changing potentially with each frame. Transport channels are the transfer services offered by Layer
1
to MAC and higher layers. The difficulty in implementing a UMTS physical layer is that transport channels have highly variable rate that can change every frame (10 ms). This requires a very adaptive memory management. The baseband modem has to store variable size packets of data corresponding to variable rate transport channels. Nevertheless, the modem is limited to by radio bandwidth. For instance, it has to handle a finite number N of 384 kbps transport channels, or alternatively 3×N 128 kbps channels, or 32×N 12 kbps channels. The memory has to be optimized to handle effectively all these cases.
One solution to this problem is proposed in U.S. Pat. No. 6,005,898. The rate is kept constant as far as the processing circuitry is concerned by duplicating signals for low data rates so that the processing circuitry receives the same data rate independent of the received data rate. This known technique makes use of time diversity to provide the extra bits at low data rates which may help to improve signal quality. However, this technique has the disadvantage that the full data rate is used independent of the received data rate. The power consumption of mobile telephones is important for battery life. Power consumption of data intensive processing tasks is largely dependent on memory accesses. As using the maximum data rate at all times means using the maximum number of data accesses to process any of the data, this solution is not optimized as to power consumption, memory usage or cost (oversize memories).
Another method is to provide a plurality of memories and to use one memory type for each data rate. This technique makes inefficient use of memory, as some of the memory may lie idle for long periods until a particular data rate is used. If the memory used is RAM which requires continuous refreshment then power consumption is not optimal. U.S. Pat. No. 5,659,698 proposes one solution to this problem. It provides a circular buffer which can be addressed by two different data sizes. A first size is determined by an offset and a second size by a sliding address. This technique has a disadvantage when the data rate varies greatly. In this case, data may be wrapped around to the beginning of the circular buffer and overwrite data which is still required. '698 states particularly that the data dealt with by the sliding address should have little or no chance of reaching the end of the buffer. To prevent this a large buffer could be used but then the use of memory is non-optimal.
There is a need for a more optimal design of circular buffer which combines a better use of memory space and optimizing power consumption while also being able to deal efficiently with data arriving at different data rates.
An object of the present invention is to provide a circular buffer and a method of operating the same which has improved optimization of power usage and memory size.
Another object of the present invention is to provide a circular buffer and a method of operating the same which has an improved performance for the temporary storing of data at variable data rates.
SUMMARY OF THE PRESENT INVENTION
The present invention provides a method of generating an address for a circular buffer in a memory, comprising the steps of:
storing a first reference value representative of a begin address of the circular buffer;
storing a second reference value representative of an end address of the circular buffer;
storing a third reference value representative of a current write address of the circular buffer;
storing a fourth reference value representative of a current read address of the circular buffer; and
protecting data stored in memory locations within the circular buffer to prevent stored data being overwritten by further data. Preferably the method further comprises the step of: storing a fifth reference value representative of the cyclic state of the circular buffer. Preferably, the fifth value is a Boolean value. The method preferably includes the step of preventing writing of data into the circular buffer depending upon the value of the fifth value. Typically, the Boolean value of the fifth value has one of two binary values, and the fifth value changes from one binary value to another as the value of either of the third and fourth value changes such as to pass the address of the end of the circular buffer. In the case of an incrementing buffer, the step of writing data into the circular buffer may be determined by the following truth table:
second value > third
fifth value = one
buffer has free memory locations
value > fourth value
binary value
and these can be allocated
third value <
fifth value = other
buffer has free memory locations
fourth < second
binary value
and these can be allocated
value
fourth value = third
fifth value = one
buffer has free memory locations
value
binary value
and these can be allocated
fourth value = third
fifth value = other
buffer is full and no memory
value
binary value
locations can be allocated
For a decrementing circular buffer a similar table applies. Typically, the data to be stored in the circular buffer is received at at least a first and a second data rate and an amount of memory space is allocated in the circular buffer in accordance with the data rate. The buffer may be implemented in any suitable memory, but especially on-chip or off-chip Random Access Memory (RAM). Typically, the circular buffer is used in a mobile telecommunications system.
The present invention provides a circular buffer having an address generator for generating an address for the circular buffer in a memory, comprising:
a first memory storage location storing a first reference value representative of a begin address of the circular buffer;
a second memory storage location storing a second reference value representative of an end address of the circular buffer;
a third memory storage location storing a third reference value representative of a current write address of the circular buffer;
a fourth memory storage location storing a fourth reference value representative of a current read address of the circular buffer; and
a memory controller for protecting data stored in memory locations within the circular buffer to prevent stored data being overwritten by further data. The circular buffer may also comprise a fif

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