Multiport data buffer having multi level caching wherein each da

Details Multiport data buffer having multi level caching wherein each da Multiport data buffer having multi level caching wherein each da

1998-02-13

2000-07-11

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 11, 710 20, 712 29, 712223, 370392, G06F 1300

Patent

active

060887443

ABSTRACT:
A three port FIFO buffer circuit uses off the shelf static RAM and dedicated shallow, e.g. 16 word, FIFOs in a multi-level caching scheme. The circuit results in multiple, reconfigurable, deep (e.g. up to 32k word) FIFO buffers. The preferred embodiment of the invention provides a buffer that comprises a bank of 32k word RAM, six dual port 16-word FIFOs, and associated sequencing logic. The sequencing logic includes RAM address registers/counter associated with each of the six FIFOs, and manages the movement of data into and out of the RAM.

REFERENCES:
patent: 5214760 (1993-05-01), Hammond et al.
patent: 5699530 (1997-12-01), Rust et al.
patent: 5805930 (1998-09-01), Rosenthal et al.
patent: 5822308 (1998-10-01), Weigand et al.
patent: 5841722 (1998-11-01), Willenz
patent: 5991299 (1999-11-01), Radogna et al.
patent: 6018778 (2000-01-01), Stolowitz
High Performance Serial Bus, IEEE Std. 1394-1995, pp. 145-153.

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