Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Patent
1998-06-17
2000-10-24
Pan, Daniel H.
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
370378, 709231, 709232, G06F 1328, G06F 1338, H04J 326
Patent
active
061381896
ABSTRACT:
A network interface transmits data packets between a host computer and a network and includes a first in first out (FIFO) buffer memory with an adaptive transmit start point determined for each data packet. The network interface receives data packets from the host computer via a peripheral component interconnect (PCI) bus. A FIFO control determines the byte length of each data packet based on the header information contained in the first few received bytes of the packet. The FIFO control also measures a minimum fill time indicating the time necessary to fill the FIFO buffer memory with a predetermined minimum amount of data necessary before transmission by the FIFO buffer memory. The FIFO control calculates the time to fill the FIFO buffer memory with each packet based on the determined length and the measured minimum fill time. The time to empty the packet from the FIFO buffer memory is also calculated based upon the length of the packet and predetermined network transmission rates. If the time to empty the packet from the FIFO buffer memory is greater than or equal to the time to fill the FIFO buffer memory, the transmit start point is set to the predetermined minimum amount; otherwise, the transmit start point is adjusted in accordance with the difference in time between filling and emptying the FIFO buffer memory with the packet, a FIFO fill rate based on the measured minimum fill time, and a coefficient that accounts for latencies in the PCI bus.
REFERENCES:
patent: 5136582 (1992-08-01), Firoozmand
patent: 5159447 (1992-10-01), Haskell et al.
patent: 5210479 (1993-05-01), Firoozmand
patent: 5257258 (1993-10-01), Birman et al.
patent: 5315580 (1994-05-01), Phaal
patent: 5398241 (1995-03-01), Witchey
patent: 5434872 (1995-07-01), Petersen et al.
patent: 5859980 (1999-01-01), Kalkunte
AMD, AM79C970 PCnet.TM.-PCI Single-Chip Ethernet Controller for PCI Local Bus, Jun. 1994, pp. 1-868--1-1033.
Advanced Micro Devices , Inc.
Pan Daniel H.
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