Multi-channel fractional clock data transfer

Details Multi-channel fractional clock data transfer Multi-channel fractional clock data transfer

2011-06-07

2011-06-07

Tsai, Henry W (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S048000

Reexamination Certificate

active

07958284

ABSTRACT:
Methods and apparatus to transfer data between one or more clock domains are described. In one embodiment, a plurality of signals corresponding to write pointers of a buffer and a read pointer of the buffer are generated. The signals corresponding to the write pointers of the buffer are to be generated based on different data patterns for transmission over different channels. Other embodiments are also claimed and described.

REFERENCES:
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patent: 2007/0011368 (2007-01-01), Wang et al.
patent: 2007/0067514 (2007-03-01), Anderson et al.
Balasubramanian, Suresh, et al., “Deterministic low-latency data transfer across Non-integral ratio”,19th International Conference on VLSI Design and 5th International Conference on Embedded Systems, Taj Krishna, Hyderabad, India, (Jan. 7, 2006), 8 pgs.
Anderson, Warren , et al., “Deterministic Operation of an Input/Output Interface”, U.S. Appl. No. 11/231,273, filed Sep. 20, 2005.

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