Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2005-03-15
2008-11-04
Sough, Hyung (Department: 2184)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S053000, C710S054000, C710S055000, C710S056000, C710S057000, C711S131000, C711S142000
Reexamination Certificate
active
07447812
ABSTRACT:
Multi-queue first-in first-out (FIFO) memory devices include multi-port register files that provide write count and read count flow-through when the write and read queues are equivalent. According to some of these embodiments, a multi-queue FIFO memory device includes a write flag counter register file that is configured to support flow-through of write counter updates to at least one read port of the write flag counter register file. This flow-through occurs when an active write queue and an active read queue within the FIFO memory device are the same. A read flag counter register file is also provided, which supports flow-through of read counter updates to at least one read port of the read flag counter register file when the active write queue and the active read queue are the same.
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Mo Jason Zhi-Cheng
Shamarao Prashant
Su Jianghui
Integrated Device Technology Inc.
Myers Bigel & Sibley & Sajovec
Rhu Kris
Sough Hyung
LandOfFree
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