Congestion aware pin optimizer
Congestion estimation for programmable logic devices
Congestion estimation for programmable logic devices
Congestion estimation for register transfer level code
Congestion-based routing with reconfigurable cross-points...
Conjunctive BDD building and variable quantification using...
Connecting verilog-AMS and VHDL-AMS components in a...
Connection block for interfacing a plurality of printed...
Connectivity-based approach for extracting layout parasitics
Connectivity-based symbol generation in wiring diagrams
Considering mask writer properties during the optical...
Constant impedance driver circuit including impedance...
Constrained detailed placement
Constrained optimization with linear constraints to remove...
Constrained register sharing technique for low power VLSI...
Constraint assistant for circuit design
Constraint based retiming of synchronous circuits
Constraint data management for electronic design automation
Constraint generating device for logic synthesis and its...
Constraint management and validation for template-based...