Constant impedance driver circuit including impedance...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000, C326S030000, C327S276000

Reexamination Certificate

active

06473886

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a constant impedance driver circuit for driving load and particularly concerns a constant impedance driver circuit which requires impedance matching with load upon transmitting a high-speed and high-frequency signal, and a method for designing the same.
BACKGROUND OF THE INVENTION
Referring to the drawings, the following will describe an embodiment of an output circuit using a conventional MOS transistor The same members in the figures are indicated by the same reference numerals and the description thereof is omitted.
Upon driving a high-speed and high-frequency signal, an output impedance of the output circuit requires impedance matching with load to prevent reflection noise on an output terminal when transmitting a signal.
FIG. 1
shows that a conventionally used output circuit connects to a transmission line serving as load.
FIG. 2
shows output current-voltage characteristics of point B shown in FIG.
1
. As shown in
FIG. 2
, the MOS transistor has a saturation region (
2
) of current. The saturation region (
2
) is characterized in that an output impedance of the MOS transistor is not constant. Particularly the low-current output circuit reaches the saturation region soon, resulting in larger irregularity in output impedance value.
As an impedance matching method of the output circuit and the load, a method is adopted for inserting a resistance Rd, which is referred to as a damping resistance, at a position of Rd in
FIG. 1
, which is a terminal of the output circuit. An optimum value of the damping resistance Rd is obtained by the following equation. As indicated in the following equation, when an output impedance value changes dynamically, the damping resistance Rd also has to change dynamically. Thus, impedance matching is extremely difficult between the output circuit and the load.
<Equation for Computing a Damping Resistance Value>
Rd
=
Zo
-
Rp
Rd
:
damping resistance
Rd
=
Zo
-
Rn
Zo
:
characteristic impedance

Rp
:
internal resistance value

Rn
:
internal resistance value

Conventionally, in order to solve such impedance mismatch between the output circuit and the load, a method has been adopted in which a MOS driver circuit forms a constant impedance output circuit.
Referring to a second conventional art (JP A5-267952), the following will discuss a conventional constant impedance output circuit.
FIG. 3
is a diagram showing the constant impedance output circuit realized by the conventional art. According to this invention, output current at an output terminal B is supplied from an input terminal A via a gate-source resistance Rgs as well. In this case, a synthetic output impedance at point B of the output terminal may be different from an output impedance, which is obtained until a MOS transistor forming the constant impedance output circuit reaches a saturation region, i.e., a value in a region which is constant in output impedance characteristic, by adding an input resistance Rgt and the gate-source resistance Rgs.
The first problem is that the second conventional art needs to supply current from a gate of the output circuit, i.e., current of a pre-stage circuit (not shown) to the output terminal B in order to keep the output impedance characteristics constant. Normally, the output circuit of the pre-stage circuit used in an LSI is much smaller in current supplying capacity than the output circuit for supplying current to external load. Therefore, in the configuration where current on the output terminal depends upon current supply from the inside of the LSI, sufficient current cannot be supplied.
The second problem is that since the current supply of the output terminal depends upon the current supply of the output circuit and the current supply from the gate, a transistor needs to be smaller in size when the low-current output circuit is realized. Generally, as the transistor is smaller in size, current-voltage characteristics of the output terminal reach the saturation region (
2
) sooner, and the current supply from the gate needs to increase accordingly. However, as earlier mentioned, the current supply from the gate depends upon the capability of the output circuit in the LSI. Hence, according to the second conventional configuration, it is difficult to realize constant impedance in the low-current output circuit.
DISCLOSURE OF THE INVENTION
In order to solve the above conventional problem, the object of the present invention is to provide a constant impedance driver circuit, in which a plurality of output circuits are connected to an output terminal of a pre-stage circuit and the switching timing is delayed between the output circuits so as to complement necessary current without changing the current supply capability of the output circuit, thereby achieving constant output impedance characteristics.
In order to achieve the above object, the constant impedance driver circuit of the present invention, which is composed of a plurality of output circuits for supplying current from an output terminal of the pre-stage circuit, is characterized in that at least one of the plurality of output circuits is provided with a switching timing delay mechanism, which includes a delay circuit for delaying the output of current behind the other output circuits, the output circuit including the delay mechanism performs switching by using the switching timing delay mechanism at a timing when current supplied from the other output circuits reaches a saturation region, the output circuits not including the delay mechanism, and constant output impedance characteristics are obtained.
Further, the constant impedance driver circuit of the present invention is characterized in that at least one of a plurality of output circuits is provided with a reference potential shift mechanism for making a shift to a higher potential in order to delay the output of current behind the other output circuits, and the output circuit including the reference potential shift mechanism performs switching by using the reference potential shift mechanism at a timing when current supplied from the other output circuits reaches a saturation region, the output circuits not including the reference potential shift mechanism, and constant output impedance characteristics are obtained.
Moreover, the constant impedance driver circuit of the present invention is characterized in that at least one of a plurality of output circuits is provided with a threshold value potential shift mechanism, which shifts a negative logic threshold value to a lower potential and shifts a positive logic threshold value potential to a higher potential than the other output circuits in order to delay the output of current behind the other output circuits, and the output circuit including the threshold value potential shift mechanism performs switching by using the threshold value potential shift mechanism at a timing when current supplied from the other output circuits reaches a saturation region, the output circuits not including the threshold value potential shift mechanism, and constant output impedance characteristics are obtained.
A method for designing a constant impedance driver circuit of the present invention includes a step of obtaining a piecewise-linear of an output terminal current-voltage curve of the output circuit and obtaining a straight line approximate to the piecewise-linear; a segment point analyzing step of finding a segment point of the output terminal current-voltage curve based on the straight line approximate to the piecewise-linear obtained in the above step; a delay time analyzing step of finding a delay time up to the segment point obtained in the above segment point analyzing step; and a step of making the delay time equal to a difference between a delayed switching time of the output circuit including the switching timing delay mechanism and a switching time of the output circuit not including the switching timing delay mechanism. The delay time has been obtained in the above delay time analyzing step.
Additionally, the

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