Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-27
2002-09-24
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C326S037000, 36
Reexamination Certificate
active
06457166
ABSTRACT:
BACKGROUNDS OF THE INVENTION
1. Field of the Invention
The present invention relates to an optimization technique for a logical circuit, and more particularly to a constraint generating device for logic synthesis which generates a delay constraint for a logical circuit having a hierarchical structure of blocks and its constraint generating method.
2. Description of the Related Art
There is a logic synthesis method disclosed in, for example, Japanese Patent Publication Laid-Open (Kokai) No. Heisei 6-266801, as the conventional technique of deciding a schematic wiring path between blocks based on a floor plan, setting a constraint at a logic synthesis according to the wiring length of a net, and executing the logic synthesis according to the set constraint.
The conventional logic synthesis method will be describe below. In the logic synthesis method, a floor plan on a logical circuit is created according to the specification of function level of a logical circuit to be synthesized logically, the wiring length of a net across blocks forming a logical circuit according to the created floor plan is estimated, and constraint information at a logic synthesis is set according to the estimated wiring length. A gate of high driving potential is generated by the first logic synthesis at the output gate of a long net across blocks, in consideration of the set constraint information. The floor plan contains location of blocks, wiring between blocks, and computation of wiring length between blocks.
In delay distribution processing, after requiring the wiring length, the delay value of a net in every block is compared with a predetermined limited value, and as for a net having the wiring length beyond the limited value or a net that is not beyond the limited value but less flexible, a logic synthesis delay constraint to the effect that the logic synthesis is performed by use of a gate of high driving potential as the output gate of the net, is generated and stored.
The conventional technique will be described in detail with reference to FIG.
5
.
FIG. 5
shows a path going from a DFF
73
within a forward block
71
to a DFF
74
within a backward block
72
through a net
80
having a delay not to be optimized, and an example of generating a logic synthesis delay constraint in the conventional technique when the clock cycle for driving the DFF
73
and the DFF
74
that may be constraint for delay distribution of the path is 12 ns.
Since the conventional technique decides the driving potential of the output gate
75
depending on the wiring length of the net
80
that is of a delay not to be optimized, a logic synthesis delay constraint is generated assuming that the wiring delay of the net
80
not to be optimized is included in the delay of the forward block
71
.
Namely, the whole delay of the forward block
71
is the total of the delay from the DFF
73
to the upstream before the input gate
76
of the backward block
72
.
Next, an example of distributing a delay distributing constraint to the forward block
71
and the backward block
72
by the ratio of each delay required in the forward block
71
and the backward block
72
is shown.
When the respective internal delays of the forward block
71
and the backward block
72
are both 4 ns and the delay of the net
80
is 8 ns, the delay of the forward block
71
becomes 12 (=4+8) ns. Since the delay distributing constraint 12 ns of the whole path is respectively divided in the forward block
71
and the backward block
72
by the ratio of the respective delays; 12:4=3:1, the forward block
71
is provided with 9 ns as a logic synthesis delay constraint and the backward block
72
is provided with 3 ns as a logic synthesis delay constraint.
Because the wiring length of the net
80
is very long, there may be the case where a path doesn't satisfy a delay constraint even if specifying the delay constraint to the effect that the driving potential of the output gate
75
in the forward block
71
is made higher in the logic synthesis process.
This case needs more detailed wiring processing such as inserting a repeater into the net
80
in the layout process. When this layout process doesn't result in satisfying the constraint, the floor plan is recomposed again.
The conventional technique, however, has the following problems.
As a first problem, a delay constraint effective in every block cannot be automatically given to a path across the blocks. This is because according as the delay not to be optimized becomes greater, vaguer logic synthesis delay constraint is distributed to the forward block which supplies a signal to the same delay not to be optimized.
As a second problem, only making the driving potential of the output gate higher is not enough to reduce the wiring delay of the net, but modification in the layout process and return to the floor planning process may frequently happen. This is because the driving potential of the output gate is limited, and when the wiring length of a net across blocks is very long, it becomes short of the driving potential.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a constraint generating device for logic synthesis and its constraint generating method capable of downsizing and speeding up a circuit to be optimized.
Another object of the present invention is to provide a constraint generating device for logic synthesis and its constraint generating method improved in efficiency by reducing the number of processes in logical circuit design.
According to the first aspect of the invention, a logic synthesis constraint generating device for generating a delay constraint for a logical circuit having a hierarchical structure of blocks, comprises
input means for receiving information of a logical circuit including the hierarchical structure divided by the block, an internal delay of each block, and a delay between the blocks, a delay distributing constraint of the logical circuit, and the target library information of the logical circuit,
storing means for storing the received information of the logical circuit, delay distributing constraint of the logical circuit, and target library information of the logical circuit,
timing analyzing means for performing a timing analysis on the information of the logical circuit and the delay distributing constraint of the logical circuit stored in the storing means, and
delay constraint distributing means of, when distributing the delay distributing constraint of the logical circuit as a logic synthesis delay constraint, receiving the ratio of each delay at a lower hierarchy excepting the delay of a circuit to be optimized for logic synthesis, and distributing the value obtained by subtracting the delay of the circuit to be synthesized logically from a constraint of a path according to the ratio of the delay of the lower hierarchy to each hierarchy as the logic synthesis delay constraint.
In the preferred construction, the logic synthesis constraint generating device further comprises floor planning means for creating a floor plan of a logical circuit to be designed, and storing wiring delay information of a net between blocks and a delay between terminals within each block into a circuit delay information storing unit as well as storing connecting information of a net between blocks into a circuit connecting information storing unit.
In another preferred construction, the logic synthesis constraint generating device further comprises floor planning means for creating a floor plan of a logical circuit to be designed, and storing wiring delay information of a net between blocks and a delay between terminals within each block into the circuit delay information storing unit as well as storing connecting information of a net between blocks into the circuit connecting information storing unit, and logic synthesis processing means for performing a logic synthesis on a circuit stored in the circuit connecting information storing unit and the circuit delay information storing unit, by use of the logic synthesis delay
Foley & Lardner
Lee Granville
NEC Corporation
Siek Vuthe
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