Constrained detailed placement

Details Constrained detailed placement Constrained detailed placement

2006-10-30

2008-12-16

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07467369

ABSTRACT:
The illustrative embodiments provide a computer implemented method which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. the process computes a weighted total wire length incremented value for the transformed data set. Further, the process continues by evaluating arrival time constraints, electrical constraints, and user configurable move limits for violations, and restoring the move cells to the original placement if a violation is found.

REFERENCES:
patent: 6080201 (2000-06-01), Hojat et al.
patent: 6415426 (2002-07-01), Chang et al.
Kahng et al., APlace: A General Analytic Placement Framework, ACM, Apr. 3-6, 2005, pp. 233-235.
Liu, Individual Wire-Length Prediction With Application to Timing-Driven Placement, IEEE, Oct. 2004, pp. 1004-1014.
Ren et al., “Hippocrates: First-Do-No-Harm Detailed Placement”, Austin Conference on Integrated Systems & Circuits 2006, May 2006, pp. 1-7.

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