Connecting verilog-AMS and VHDL-AMS components in a...

Details Connecting verilog-AMS and VHDL-AMS components in a... Connecting verilog-AMS and VHDL-AMS components in a...

2007-07-31

2007-07-31

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C703S013000

Reexamination Certificate

active

10952222

ABSTRACT:
A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal design comprises one or more VHDL-AMS and Verilog-AMS components, including a first VHDL-AMS component and a first Verilog-AMS component. The method further includes receiving a predetermined set of connection rules, resolving incompatibilities between the first VHDL-AMS component and the first Verilog-AMS component in accordance with the predetermined set of connection rules, and connecting the first VHDL-AMS component to the first Verilog-AMS component.

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P.Frey et al., “Verilog-AMS: Mixed-Signal Simulation and Cross Domain Connect Modules,” 2000 IEEE, pp. 103-108.
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