Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-05-20
2002-08-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06438729
ABSTRACT:
COPYRIGHT NOTICE
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the xerographic reproduction by anyone of the patent document or the patent disclosure in exactly the form it appears in the U.S. Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights.
APPENDIX
A microfiche appendix of one sheet with 64 frames is included in this application.
BACKGROUND OF THE INVENTION
The present invention relates to the field of designing and fabricating integrated circuits. More specifically, the present invention relates to a system for extracting layout parasitics.
Integrated circuits are electrical circuits comprised of transistors, resistors, capacitors, and other components on a single semiconductor “chip” in which the components are interconnected to perform a given function such as a microprocessor, programmable logic device (PLD), electrically erasable programmable memory (EEPROM), random access memory (RAM), operational amplifier, or voltage regulator. A circuit designer designs the integrated circuit by creating a circuit schematic indicating the electrical components and their interconnections. Generally, designs are simulated by computer to verify functionality and ensure performance goals are satisfied.
Integrated circuits are typically fabricated using a photolithography technique where a semiconductor material is selectively exposed to light by using masks. the exposed or unexposed areas of the semiconductor material are processed to form the features of the integrated circuit such as transistors and interconnects. Processing continues layer by layer until all the layers of the integrated circuit are formed.
Each mask contains the geometries for a particular layer of the integrated circuit. For example, a geometry may be used to form the metal interconnection between two transistors. To generate the masks for an integrated circuit, the circuit designer first creates a layout of the electrical components that implements the design in a circuit schematic. This layout is generally contained in a computer database having all the geometries for all mask layers. From this computer database, the masks are generated.
The layout of an integrated circuit contains parasitic resistances and capacitances from the interconnections and devices. The values of these parasitics depend on the process parameters, shape and dimensions of a particular geometry, and relationship of a particular geometry to other geometries. These parasitics affect the performance and possibly the functionality of an integrated circuit. Consequently, during the design phase of an integrated circuit, these parasitics are extracted from a layout and taken into consideration during circuit simulation. Two conventional approaches for extracting layout parasitics are the full-chip Boolean operation method and direct simulation method.
The full-chip Boolean operation method extracts full-chip layout parasitics. A user must specify the Boolean operations that are to be performed on the layout layers. The user must also provide a table of process parameters and coefficient values. In order to specify these Boolean operations, the user undertakes the sometimes intricate task of writing custom equations for each design. As integrated circuits continue to increase in size, functionality, and complexity, so does the time and effort required to develop the correct Boolean operation.
The approach of using Boolean operations to calculate resistance and capacitance parasitic data was developed over fifteen years ago. The simple formulas generated by this approach were previously sufficient. However, as feature sizes of VLSI chips approach 0.3 micron and smaller, this approach cannot reliably extract layout parasitics information accurately enough to meet the performance requirements for interconnect simulations and timing analysis of present-day high-performance VLSI designs.
This full-chip Boolean operation method is typically performed as a batch extraction and uses the command file to extract parasitic capacitances for the entire integrated circuit. Consequently, this becomes very time consuming because the approach computes parasitic resistance and capacitance values for geometries in total isolation.
A user who desires only to extract data on a particular net, such as a clock net, must extract an entire integrated circuit to get the desired information. After this information is obtained and analysis is performed on the net, the user will want to make changes if the targeted performance goal is not achieved. After any changes are made, a user will need to extract the entire design once again to perform the required analysis. These design iterations can take weeks to complete. Even if this method is successfully used, the user cannot generate a complete distributed resistance and capacitance (RC) netlist (which provides greater accuracy) suitable for timing or interconnect simulation.
The above approach also uses textual data to pass information to and from the extraction process, which is not a format directly compatible with many software programs. Another disadvantage of the full-chip Boolean net is that a user cannot select a net for extraction. Furthermore, there is no graphical interface or viewer that permits a user to view the design or highlight and select a net or block for extraction of the parasitic data. A user must extract the entire design each time a change is made to the layout or extraction is required on any part of the chip.
The direct simulation method has been implemented to extract small-area layout parasitics. It is based on a user specifying a particular area or region of an integrated circuit for extraction. This area is then divided into smaller areas which a field solver can simulate. However, a drawback is that the field solver takes a substantial amount of time to simulate even for relatively small areas. Consequently, this approach is limited to small-area parasitic extraction. Although some improvements have been made in the art of field solvers, extraction time is still excessive. Furthermore, a field solver approach cannot generate a complete net-by-net distributed RC netlist including transistor parameter timing or power simulation.
The direct simulation method is also not net-based. The direct simulation method performs calculations only on selected areas, regions, geometries, or structures to extract, but not a net. A net, such as a clock net, may extend throughout an integrated circuit; it would not be practical for a field solver to consider such a large area.
As the feature sizes of integrated circuits are continually shrinking, operating frequencies of integrated circuits are increasing, and the number of transistors per integrated circuit is increasing, the performance of integrated circuits depend more on layout parasitics, especially the layout parasitics of the interconnect. Furthermore, since the number and complexity of integrated circuits continues to increase, there is a need for better, faster, more accurate, and improved layout parasitics extraction methods.
SUMMARY OF THE INVENTION
The present invention is a layout parasitic extraction system. In particular, the layout parasitics are extracted using a connectivity-based approach. This will allow extraction of layout parasitics on a net-by-net basis. The system generates a connectivity-based database where geometries of the layout are organized by nets of the circuit schematic or netlist. Using this connectivity database, parasitics for one or more nets of the integrated circuit are extracted. The types of parasitics extracted include resistances and capacitances. The user may select which nets are to be extracted; the unselected nets will not be extracted.
The system may be coupled with layout network connectivity extraction (NCE) or layout versus schematic checker (LVS) to allow net-by-net layout parasitic extraction under user input without again requiring whole chip connectivity ex
Garbowski Leigh Marie
Synopsys Inc.
Townsend and Townsend / and Crew LLP
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