Congestion estimation for programmable logic devices

Details Congestion estimation for programmable logic devices Congestion estimation for programmable logic devices

2006-12-05

2006-12-05

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07146590

ABSTRACT:
A method of estimating congestion for a programmable logic device can include calculating a number of fan-in paths for each resource in the programmable logic device and calculating a number of fan-out paths for each resource in the programmable logic device. For each resource of the programmable logic device, a number of paths having different path characteristics can be determined and a probability can be assigned thereto. One or more measures of congestion can be computed according to the determining step.

REFERENCES:
patent: 7086023 (2006-08-01), Visweswariah
patent: 2004/0243964 (2004-12-01), McElvain et al.

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