Standard semiconductor cell with contoured cell boundary to incr
Static random access memory device and manufacturing method ther
Stochastic assembly of sublithographic nanoscale interfaces
Strained complementary metal oxide semiconductor (CMOS) on...
Strained complementary metal oxide semiconductor (CMOS) on...
Stressed field effect transistors on hybrid orientation...
Structure and method for failure analysis in a semiconductor...
Structure and method of making strained channel CMOS...
Structure and method of making three finger folded field...
Structure for connecting to integrated circuitry
Substrate contact for gate array base cell and method of forming
Substrate for an electronic power circuit, and an electronic...
Symmetrical multi-layer metal logic array employing single gate
Symmetrical multi-layer metal logic array with continuous substr
Symmetrical multi-layer metal logic array with continuous substr
Symmetrical multi-layer metal logic array with extension portion
System and method for programming a memory cell
System and method for providing scalability in an integrated...
System with meshed power and signal buses on cell array
System with meshed power and signal buses on cell array