Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2003-08-26
2004-07-27
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S202000, C257S204000, C257S205000, C257S276000, C257S272000, C257S280000, C257S283000
Reexamination Certificate
active
06768143
ABSTRACT:
BACKGROUND OF INVENTION
The present invention relates to semiconductor integrated circuits and more specifically to the layout of semiconductor devices, especially for a semiconductor memory.
Operational performance and conservation of integrated circuit “chip” area are considerable in the design of circuits. It is desirable to reduce chip area because circuit designs that occupy smaller chip areas generally offer higher interconnect performance and speed. Circuit designs that occupy large chip areas typically have longer interconnect wiring which degrades performance. Longer wires have higher parasitic capacitance and resistance, either of which increases delay.
Because of their high integration density, dynamic random access memories are a favored way of storing large amounts of information for ready access within a computing system. A typical dynamic random access memory (DRAM)
10
consists of a data storage array
12
, a bit line access system
14
, a word line select system
16
, control logic
18
, and an external interface
20
, as shown in FIG.
1
.
FIG. 2
provides a detailed illustration of a DRAM
110
corresponding to DRAM
10
shown in FIG.
1
. As shown in
FIG. 2
, data storage array
112
corresponds to data storage array
12
shown in FIG.
1
and block
116
corresponds to wordline select system
16
shown in FIG.
1
. The bitline (data) access system
14
, control logic
18
and external interface
20
are not shown in FIG.
2
.
As used herein, the terms “horizontal” and “horizontally”, “vertical” and “vertically” describe directions generally parallel to the main surface of a semiconductor substrate, horizontal being the direction in which wordlines extend across the substrate, and vertical being the direction in which bitlines extend across the substrate. As shown in
FIG. 2
, the bitlines
100
,
102
and
104
run vertically in columns across the data storage array
112
, traversing the wordlines
120
,
122
and
124
which run horizontally in rows across the data storage array
112
. Data storage cells (e.g. Data Cell (
0
,
0
) ) are provided at the intersections between the bitlines and the wordlines. The wordlines of the data storage array
112
have a pitch
130
. Pitch is defined as the dimension occupied by a recurring feature and its spacing to the next recurring feature in a line of such features.
It is desirable that the pitch
130
of wordlines in the data storage array
112
be kept as small as possible for the following reasons. First, the data storage array
112
should store as much information as possible within a given area of an integrated circuit (hereinafter, a “chip”). Accordingly, data storage cells and the wordlines and bitlines that provide access to the data stored therein should be packed as closely together as possible.
Second, the wordline pitch
130
should be made small because the length of the bitlines in the data storage array
112
is directly controlled by the wordline pitch. The length of the bitlines spanning a data storage array
112
should be made as short as possible in order to best transfer signals on each bitline, e.g. bitline
100
, to and from a data cell (e.g. Data Cell (
0
,
0
)
106
) of the data storage array
112
. Parasitic bitline capacitance, which affects both the speed and the validity of signals transferred on a bitline, increases with the length of the bitline. Keeping bitlines short reduces the parasitic capacitance and improves the quality of the bitline signal.
As further shown in
FIG. 2
, the word lines in the data storage array
112
are driven by a word line select system
116
. Each wordline is activated by a corresponding driver, upon the driver receiving an enabling decoded input from wordline select decoder
117
and decoded power supply input for the particular bank. For example, wordline
120
is activated by a driver
150
when enabling decoded input
119
is received from wordline select decoder
117
together with a decoded power supply input BK
2
for a bank
2
of the data storage array
112
.
FIG. 3
is a diagram illustrating the timing of operations within the data storage array
112
. As illustrated in
FIG. 3
, an operation to read a data bit from or write a data bit to a data cell is provided in three phases. In a first phase,
300
, bitlines are precharged and equalized by signal EQ to a desirable voltage. Thereafter, at the start of the next phase
310
, EQ is lowered and the wordline is activated, as indicated by the rising signal WL. During this phase, the activated wordline turns on transistors of data cells, which results in the transfer of stored charge from storage capacitors of the data cells to bitlines. The bitlines, in turn, transfer the charge retrieved from data cells as data bit signals to sense amplifiers.
At the start of the next phase
320
, the transfer of the data bit signal from the data cell to sense amplifier is about complete. During this phase
320
, which commences with the rising SET signal, each sense amplifier amplifies a data bit signal for the purpose of outputting the data bit from the DRAM, and/or for restoring the data bit to the data cell of the data storage array
112
.
During phase
320
, the data bits accessed from data cells by the activated wordline are written back, i.e. restored to the data cells. The data access cycle is now completed. Accordingly, the wordline is now deactivated, as marked by the falling signal WL, and a precharge phase
330
begins for a new data access cycle.
The cycle time for accessing the data stored in a data cell is the sum of the length of phases
300
,
310
and
320
. As apparent from the above description, two factors contribute heavily to the cycle time.
The first is the length of time, i.e., the duration of the phase
310
, that is required to transfer data bit signals from storage capacitors of data cells to sense amplifiers. The duration of this phase
310
is influenced heavily by the amount of parasitic capacitance of the bitline. The time delay for a data bit signal to be transferred from a data cell to a sense amplifier is measured in terms of an “RC” delay determined by the resistance “R” of the bitline multiplied by the capacitance “C” of the bitline. The resistance and parasitic capacitance of a bitline are directly proportional to the length of the bitline. Accordingly, the length of bitlines must be kept as small as practicable in order to provide desirably short cycle time.
In addition to determining the RC delay, the amount of the bitline capacitance also affects the maximum voltage which appears on the bitline at the sense amplifier during the phase
310
in which charge is transferred from data cell to sense amplifier. The greater the bitline capacitance, the smaller the voltage appears at the sense amplifier. Thus, high bitline capacitance increases the chance that the data bit signal is amplified incorrectly, for example, that a signal from a data cell storing a value of “1” is amplified as a “0” or vice versa. To counteract signal loss due to increased bitline capacitance, the voltage stored in the data cell must be increased. Such increase typically requires increasing the duration of phase
320
in order to lengthen the write-back time for storing a data bit signal from sense amplifier to data cell. This also increases cycle time.
A second factor contributing to the length of the cycle time is the transition time of the wordline WL. As shown in
FIG. 3
, at the beginning of the signal development phase
310
, the wordline WL rises from an deactivated level to an activated level over a rising transition time
340
. The wordline remains at the activated level throughout phases
310
and
320
and then falls back to the deactivated level over a falling transition time
350
. These transition times represent wasted time because the voltage level of the wordline is then intermediate between activated and deactivated levels and therefore cannot be relied upon for operations. Thus, the rising and falling transition times of the wordline represent wasted time that contributes directly to
Fredeman Gregory J.
Golz John W.
Hanson David R.
Kim Hoki
Erdem Fazli
Neff Daryl K.
Schnurmann H. Daniel
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