Structure and method for failure analysis in a semiconductor...

Details Structure and method for failure analysis in a semiconductor... Structure and method for failure analysis in a semiconductor...

2005-11-30

2008-12-23

Le, Thao X (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

C257SE21521

Reexamination Certificate

active

07468530

ABSTRACT:
In a method and structure for semiconductor failure analysis, the structure comprises: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array; wordlines arranged on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a first direction; and bitline structures on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a second direction, wherein the bitline structures are configured in different patterns in each of the plurality of analytic fields.

REFERENCES:
patent: 5444012 (1995-08-01), Yoshizumi et al.
patent: 5937290 (1999-08-01), Sekiguchi et al.
patent: 2003/0034558 (2003-02-01), Umemura et al.
patent: 2003/0122160 (2003-07-01), Houston et al.
patent: 2004/0105327 (2004-06-01), Tanno
patent: 07-037988 (1995-02-01), None
patent: 09-064122 (1997-03-01), None
patent: 09-321245 (1997-12-01), None
patent: 2003-133377 (2003-05-01), None
patent: 2004-178724 (2004-06-01), None
patent: 10-2003-0050651 (2003-06-01), None
patent: 10-2004-0047709 (2004-06-01), None

Affiliated with

Also associated with

Rating

Structure and method for failure analysis in a semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Structure and method for failure analysis in a semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Structure and method for failure analysis in a semiconductor... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4025334