Device having enhanced stress state and related methods
Device having improved surface planarity prior to MRAM bit...
Device having improved surface planarity prior to MRAM bit...
Device having recessed spacers for improved salicide...
Device having reduced diffusion through ferromagnetic materials
Device having spacers for improved salicide resistance on...
Device having thin first spacers and partially recessed...
Device having two perovskite crystalline layers that shows...
Device improvement by lowering LDD resistance with new...
Device including a resistive path to introduce an equivalent...
Device layer of a silicon-on-insulator structure having...
Device layout to improve ESD robustness in deep submicron...
Device method for enhanced avalanche SOI CMOS
Device providing protection against electrostatic discharges...
Device sensitive to a movement comprising at least one...
Device structure and manufacturing method using HDP...
Device structure and method for reducing silicide encroachment
Device structure and method for reducing silicide encroachment
Device structure for high voltage tolerant transistor on a 3.3 v
Device structure of RF LDMOS with trench type sinker