Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-06
2004-06-15
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S357000
Reexamination Certificate
active
06750517
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to ESD protection circuits and more particularly to designs for minimizing damage at drain contacts around the ends of the MOS multiple fingers.
2. Description of Related Art
In the design of ESD protection circuits, grounded-gate MOS devices are usually used as the ESD protection devices to bypass the ESD current when ESD overstress is applied to the I/O pins of an IC. For sustaining a large ESD current the channel width of the protection MOS transistor should be large enough. With a large device dimension, the ESD MOS transistors are traditionally implemented with multiple fingers to bypass the ESD current efficiently.
However ESD damaged areas caused by contact spiking are often located at the drain contacts around the two ends of the multiple drain fingers is more serious in machine model ESD tests due to the faster rise time and the larger current of the ESD pulse.
A schematic diagram of a popular input ESD protection circuit is shown in
FIG. 1
, which is used to bypass the ESD overstress from the I/O pins to VDD/VSS power rails. In this design, a PMOS transistor (M
p
) with large channel width is connected between the VDD power rail and the PAD. The gate of the PMOS transistor is connected to VDD power rail through a resistor R
p
. PMOS transistor M
p
is turned off during the normal operating condition. Resistor R
p
is used to prevent the gate oxide breakdown of transistor M
p
in an ESD overstress condition. The parasitic lateral p-n-p Bipolar Junction Transistor (BJT) of transistor M
p
is also shown in FIG.
1
. The source and drain P+ diffusions of transistor M
p
are the emitter and collector of the BJT, respectively. The base of the BJT is formed by the N-well and is connected to VDD power line through the parasitic N-well resistance R
w
. The parasitic lateral p-n-p BJT is used to bypass the ESD current when ESD overstress is across PAD and VDD node. An NMOS transistor (M
N
) with large channel width is used to bypass the ESD current when ESD overstress is across PAD and VSS node. The gate of the NMOS transistor is connected to VSS power rail through a resistor R
N
. M
N
is turned off during the normal operating condition. R
N
is used to prevent the gate oxide breakdown of M
N
in ESD overstress condition. The parasitic lateral n-p-n BJT of M
N
is shown in the figure, too. The source and drain N+ diffusions of M
N
are the emitter and collector of the BJT, respectively. The base of the BJT is formed by the p-substrate and is connected to VSS power line through the parasitic substrate resistance R
sub
.
For implementing the PMOS transistor M
p
and NMOS transistor M
N
in
FIG. 1
with large channel width, the multiple-finger layout style is usually applied in such ESD protection devices.
The multiple-finger layout style of an ESD-protection NMOS transistor device is drawn in FIG.
2
. The parameters of layout geometry should be designed appropriately to improve the ESD level of ESD-protection device. For example, the distance of drain contact to polysilicon-gate edge and the distance of source contact to polysilicon-gate edge are two important layout parameters.
These two parameters are termed as ‘d’ and ‘s’ in
FIG. 2
, respectively. The symmetric layout on the multiple fingers of the MOS transistor is very important for the turn-on uniformity of these fingers during ESD stress.
Recently, there were several layout approaches proposed to improve the ESD robustness of the ESD-protection devices [1-8]. Different layout styles of a same ESD-protection device will perform different ESD robustness. The ESD performance is very strongly dependent on layout. Therefore, improving ESD performance through appropriate layout style is very important for ESD design.
FIG. 3
is a layout technique reported in [2] [4] to improve the ESD robustness of the ESD-protection device. In this implementation, the P+ pick-up with contacts are inserted between the source sides of two neighboring NMOS transistor fingers. These P+ pick-up are connected to VSS power rail through the contacts. In this implementation, the substrate resistance, R
sub
, of each MOS transistor finger is nearly the same, therefore the turn-on uniformity among the MOS multiple fingers can be improved. This is an example of improving ESD performance by layout technique.
But, there are still some problems in the traditional multiple-finger layout style. The traditional finger-type layout for NMOS is illustrated in FIG.
2
. Its cross-sectional view along the line
4
-
4
′ in
FIG. 2
is shown in
FIG. 4
, which is demonstrated in a p-substrate bulk CMOS process. There are two important ESD-related spacings in this traditional finger-type layout, which are ‘d’ and ‘s’ as we mentioned previously.
Except these two parameters, another important ESD-related spacing, denoted as ‘G
0
’ in
FIG. 2
, often degrades ESD robustness of CMOS I/O circuits.
FIG. 5
is a schematic cross-sectional view along the line
5
-
5
′ in
FIG. 2
prior art device showing the ESD peak-discharging effect of the finger's end of the finger-type layout.
FIG. 5
includes a plot for explaining the ‘G
0
’ spacing. In
FIG. 5
, there exists a parasitic diode D
1
, between the P+ diffusion and the N+ diffusion of the drain. The spacing from the edge of p+ diffusion to the edge of drain N+ diffusion is termed as ‘G
0
’. If this spacing is smaller than that from the drain contact to its source contact, the diode D
1
will be first broken down due to the ESD peak-discharging effect before the NMOS drain is broken down. Even if the spacing ‘G
0
’ is larger than the spacing ‘d’ in the finger-type NMOS device, the ESD hot spot may still occurs at the drain edge due to the peak structure at the end of the finger of the finger-type layout. This phenomenon occurs often in the machine-model (MM) ESD test. The machine-model ESD stress of 200V has a higher and faster ESD current than that of the human-body-model (HBM) ESD stress of 2000V. In the fast ESD transition, not only the spacing effect but also the peak-discharging effect can cause the ESD damage located on the end of the drain finger.
For solving the problems of finger-type layout mentioned above, some other different layout styles of the ESD protection device were proposed to improve the ESD robustness [6-8]. The square-type [6], hexagon-type [7], and octagonal-type [8] layouts were used to drawn the ESD protection devices. The square-type layout style, which is used to realize the MOS device [6], is plotted in FIG.
6
. In
FIG. 6
, there are four small-dimension square cells to form a large-dimension NMOS device. The polysilicon gate in each square cell is drawn in a square ring. The contacts at the source region are placed in a square-type arrangement. Outside the NMOS device, there are double guard rings. All the layout elements in a square cell, including the contacts, have to be placed as symmetrically as possible to ensure uniform ESD current flow in the NMOS device to increase its ESD reliability. By using the square-type layout design, there is no ‘G
0
’ spacing in the square-type output transistors. Moreover, no parasitic diode directly closes to the drain edge in the square-type layout, so the ESD robustness of output transistors is not degraded by the ESD peak-discharging effect as shown in
FIG. 5
with the traditional finger-type layout. By the square-type layout proposed in [6], the layout area of CMOS output transistors can be effectively reduced but the driving capability is higher and the ESD reliability is better. Because the output transistors realized by more symmetrical device structures, the transistors can be more uniformly triggered during the ESD-stress events. This is another example of improving ESD robustness by modifying layout style of the ESD protection device.
Although some approaches had been proposed to improve the turn-on uniformity of differe
Ker Ming-Dou
Wu Mau-Lin
Ackerman Stephen B.
Jones II Graham S.
Nadav Ori
Saile George O.
Taiwan Semiconductor Manufacturing Company
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