Device having improved surface planarity prior to MRAM bit...

Details Device having improved surface planarity prior to MRAM bit... Device having improved surface planarity prior to MRAM bit...

2008-05-20

2008-05-20

Tsai, H. Jey (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S421000, C257S422000, C257SE21665

Reexamination Certificate

active

07375388

ABSTRACT:
The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

REFERENCES:
patent: 5354712 (1994-10-01), Ho et al.
patent: 5940319 (1999-08-01), Durlam et al.
patent: 6110648 (2000-08-01), Jang
patent: 6174737 (2001-01-01), Durlam et al.
patent: 6181013 (2001-01-01), Liu et al.
patent: 6211090 (2001-04-01), Durlam et al.
patent: 6555858 (2003-04-01), Jones et al.
patent: 6709874 (2004-03-01), Ning
patent: 2002/0098705 (2002-07-01), Low

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