Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-04
2003-01-21
Leke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S900000
Reexamination Certificate
active
06509618
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor devices. More particularly, the present invention relates to a method and device for improved resistance on gate electrodes. Specifically, the present invention relates to a method and device for improved salicide resistance on polysilicon gates.
BACKGROUND OF THE INVENTION
Transistors are commonly used in semiconductor circuitry to control current flow. For example, a transistor can be used as a switching mechanism to allow the flow of current between a source and a drain region in a circuit when a certain threshold voltage is met. Transistors generally include a gate electrode that allows or prevents the flow of current in the transistor based on applied voltage.
FIG. 1
a
shows a cross-sectional view of a conventional gate electrode
100
formed on a substrate
110
, the underlying structure of which is not shown. It should be noted that the figures are merely illustrative and have been simplified for clarity purposes. A thin insulative layer
120
is formed on the substrate
110
to act as a barrier between the substrate
110
and the conductive portions of the gate electrode
100
. An example of an insulative layer
120
can be an oxide layer, such as silicon dioxide (SiO
2
). Formed on the insulative layer
120
is a gate layer
130
. An example of a gate layer
130
can be a polysilicon layer. Formed on the gate layer
130
is a conductive layer
160
. An example of a conductive layer
160
can be a polycide layer, such as titanium salicide (TiSi
2
). When a threshold voltage is applied to the gate layer
130
by the conductive layer
160
, current will flow through the gate layer
130
. Often insulative spacers
140
and
150
are formed to each side of the gate layer
130
to prevent transfer of current between the gate layer
130
and surrounding structures in the semiconductor.
In semiconductor circuit design, frequently, gate electrodes are designed in long continuous lines on the semiconductor substrate to efficiently provide current to several transistors in a circuit. Currently, improved semiconductor transistor performance is being achieved through device scaling in which the gate layer widths are being reduced from 0.20 &mgr;m to 0.15 &mgr;m and below (sub-0.15 &mgr;m). As the gate layer width dimensions decrease, so do the conductive layer line widths formed above them.
When the gate layer widths decrease below 0.20 &mgr;m, current process techniques produce conductive lines with sharply increasing resistance. This is detrimental to the efficiency of the semiconductor, as higher resistance decreases the speed of the semiconductor circuitry. Additionally, process yields drop due to defective conductive line formation reducing manufacturing output. These problems have been particularly noted in current fabrication processes where titanium salicide (TiSi
2
) is formed as the conductive layer in a polysilicon gate.
FIG. 1
b
illustrates a cross-sectional view of a conventional gate electrode
100
formed on a substrate
110
, the underlying structure of which is not shown. An example of a gate electrode
100
can be a polysilicon gate electrode. Formed on the substrate
110
is an insulative layer
120
. An example of an insulative layer
120
can be an oxide. Formed on the insulative layer
120
is a conductive gate layer
130
. An example of a gate layer
130
is a polysilicon layer. Formed on the gate layer
130
is a conductive layer
160
. An example of a conductive layer
160
can be a polycide, such as titanium salicide. Insulative spacers
140
and
150
are formed adjacent to the gate layer
130
and conductive layer
160
to prevent current flow between the gate layer
100
and surrounding structures.
During formation of the conductive layer
160
, components from underlying gate layer
130
often out diffuse into a reactant layer that is used to form the conductive layer
160
. For example, silicon components of an underlying gate layer
130
may out diffuse into the conductive layer
160
. This out diffusion results in a conductive layer
160
wider than the gate layer
130
. When the gate layer
100
width is decreased below 0.20 &mgr;m, the conductive layer
160
becomes stressed by its enclosure between the side walls of the spacers
140
. This results in increased resistance in the conductive layer
160
. Increased resistance in the conductive layer directly impacts the quality of the semiconductor circuit. The circuit becomes inefficient and circuit failure or device failure may occur.
Another result of decreasing the gate line widths below 0.20 &mgr;m is a decrease in process yields. This is due to non-formation of the conductive layer. This is attributed to the reduced reaction area, or nucleation sites, available at such small dimensions. The reduced dimensions of the gate layer reduces nucleation sites on which the conductive layer can form during processing. Using current process techniques, if sufficient nucleation sites are not provided, the conductive layer often won't form. This directly impacts the semiconductor manufacturer by reducing output.
Based on the above described problems, it would be desirable to have a method and/or device which will improve the polycide resistance in polysilicon gate widths below 0.20 &mgr;m.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a method and a device which improves polycide resistance in gate electrode widths below 0.20 &mgr;m. The invention provides several embodiments one embodiment of which is described below.
In one embodiment of the present invention there is provided a gate electrode comprising a thin insulative layer. A gate layer is formed on the thin insulative layer. A conductive layer is formed on the gate layer. Thick first spacers are formed adjacent to opposite sides of the gate layer. Thick second spacers are formed adjacent to the thick first spacers. The thick first spacers are recessed to create an open space between the gate layer and thick second spacers.
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International Search Report, PCT/US99/26175, Apr. 4, 2000.
Nakayama, T., et al., “Excellent Process Control Technology for Highly Manufacturable and High Performance 0.18 mm CMOS LSIs” IEEE, 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 146-147.
International Search Report, PCT/US 99/26175, Nov. 4, 1999.
Ghani Tahir
Jan Chia-Hong
Keating Steven J.
Myers Alan
Tsai Julie A.
Chen George
Intel Corporation
Leke Steven
Vu Hung Kim
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