Semiconductor memory device having sub dummy bit line and sub du

Semiconductor memory device having switching and memory cell...

Semiconductor memory device in which a BIT line pair having a hi

Semiconductor memory device including clock-independent...

Semiconductor memory device including sense amplifier...

Semiconductor memory device including sense amplifier...

Semiconductor memory device of alternately-activated open bit-li

Semiconductor memory device of hierarchical bit-line architectur

Semiconductor memory device performing last in-first out operati

Semiconductor memory device permitting improved integration...

Semiconductor memory device provided with sense amplifier capabl

Semiconductor memory device using sense amplifiers in a dummy ce

Semiconductor memory device with a redundant memory cell array

Semiconductor memory device with a reference potential generator

Semiconductor memory device with controllable operation...

Semiconductor memory device with dummy word line

Semiconductor memory device with ferroelectric device

Semiconductor memory device with folded bit line structure suita

Semiconductor memory device with high-speed sense amplifier

Semiconductor memory device with improved cell arrangement