Semiconductor memory device with a redundant memory cell array

Details Semiconductor memory device with a redundant memory cell array Semiconductor memory device with a redundant memory cell array

1990-11-19

1992-06-23

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365226, 365190, 36518905, G11C 1140

Patent

active

051249499

ABSTRACT:
A semiconductor memory device with a redundant memory cell array includes two transfer gate circuits. The first transfer gate circuit transfers a signal selected from two signals, one of which from a first detecting circuit for detecting a selection of a redundant memory cell array to substitute an ordinary memory cell which includes a faulty memory cell, the other from a second detecting circuit for detecting an address of the ordinary memory cell array including the faulty memory cell. The second transfer gate circuit transfers a signal transferred from the first transfer gate circuit when the semiconductor memory device is not in a write enable state. When the semiconductor memory device is not in a write enable state, it is possible to detect a selection of the redundant memory cell array or an address of the ordinary memory cell array including the faulty memory cell, by monitoring the state of an output terminal of the semiconductor memory cell.

REFERENCES:
patent: 4982364 (1991-01-01), Iwahashi

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