Semiconductor memory device including clock-independent...

Details Semiconductor memory device including clock-independent... Semiconductor memory device including clock-independent...

2002-08-29

2003-11-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S208000, C365S189090, C365S203000, C365S195000

Reexamination Certificate

active

06643203

ABSTRACT:

CROSS-REFERENCE TO THE RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-298506, filed Sep. 27, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a techniques used in a leakage test for a semiconductor memory device such as a flash EEPROM (Electrically Erasable and Programmable Read Only Memory).
2. Description of the Related Art
In recent years, microcomputer systems embedded flash memory have been used. The flash memory embedded into a microcomputer operates in sync with the system clock that controls the microcomputer system.
The memory sense circuit system of a conventional clock-synchronous flash memory will be described using
FIG. 1
, which is a block diagram of that flash memory.
As shown, the flash memory, indicated at
200
, includes a read control circuit CNTROL
1
, a level control circuit LVLGEN, a read column decoder RDCOLDEC, a write column decoder WRCOLDEC, a column decoder COLDEC, a row decoder ROWDEC, an erase control circuit CNTROL
2
, and 32 memory blocks BLK.
The read control circuit CNTROL
1
is responsive to a system clock CLK, an address select signal ROMCS and an output enable signal OE, which are supplied from the CPU in the microcomputer, to output a precharge signal PRCV, a data latch clock signal ACT
2
, and an output control signal CSRD. The arrangement of the read control circuit CNTROL
1
is illustrated in FIG.
2
A. As shown, the read control circuit CONTROL
1
comprises two NAND gates
300
-
1
and
300
-
2
, two buffers
310
-
1
and
310
-
2
, and two inverters
320
-
1
and
320
-
2
. The NAND gate
300
-
1
performs a logical NAND operation on the address select signal ROMCS and the system clock CLK. The NAND gate
300
-
2
performs a logical NAND operation on the address select signal ROMCS and the inverse of the system clock CLK from the inverter
320
-
1
. The precharge signal PRCV is the buffered signal of the output of the NAND gate
300
-
1
from the buffer
310
-
1
. The data latch clock signal ACT
2
is the inverse of the output signal of the NAND gate
300
-
2
from the inverter
320
-
2
. The output control signal CSRD is the buffered signal of the output enable signal OE from the buffer
310
-
2
.
The level control circuit LVLGEN is responsive to the control signal PSV to produce a level control signal LVLDWN.
The read column decoder RDCOLDEC is responsive to address signals A
3
and A
2
and a read signal RD to make a selection from four read column select lines SR
0
to SR
3
.
The write column decoder WRCOLDEC is responsive to address signals A
3
, A
2
and a write signal WR to make a selection from four write column select lines SWR
0
to SWR
3
.
The column decoder COLDEC is responsive to address signals A
6
to A
4
to make a selection from eight column select lines S
0
to S
7
.
The row decoder ROWDEC is responsive to address signals A
18
to A
7
to make a selection from (n+1) word lines WL
0
to WLn.
The erase control circuit CNTROL
2
is responsive to an erase signal ERASE to produce erase signals ERSV and ERSPLS.
The memory block BLK includes a memory cell array ARRAY, a column selector CS, an erase switching circuit ERS_SLCT, a write control circuit PRGCNT, a write circuit WRITE, a read circuit READ, and a reference voltage generating circuit REF_VOL.
The memory cell array ARRAY has memory cells (flash cells) MC arrayed in a matrix form. The memory cells have their gates connected to the word lines WL
0
to WLn and their sources connected together to a common source line SL, which in turn is connected to the erase switching circuit ERS_SLCT. The drains (bit lines BL) of the memory cells are connected to the column selector CS.
The erase switching circuit ERS_SLCT operates based on the erase signals ERSV and ERSPLS from the erase control circuit CONTROL
2
and drives the source line to a high potential at the time of erasing memory cells and to ground potential otherwise.
The column selector CS is responsive to signals on the column select lines S
0
to S
7
to select one of the bit lines BL.
The write circuit WRITE has a write control circuit PRGCNT, a write transistor
210
, and a number of select transistors
220
. The write control circuit PRGCNT is responsive to a write signal WR from the CPU and write data carried to a data bus DBUS to output a write control signal PD. The transistor
210
is a pMOS transistor having its gate supplied with the write control signal PD and its source connected to a high-potential voltage source. Though only one is shown, the select transistors
220
have their gates connected to the write column select lines SWR
0
to SWR
3
, their sources connected to the drain of the write transistor
210
and their drains connected to bit lines BL selected by the column selector CS. At write operation, a potential corresponding to write data is applied to a bit line BL selected by the column selector CS and the select transistor
220
.
The read circuit READ has a plurality of select transistors
230
, a bias control transistor
240
, a bit-line precharging transistor
250
, a sense amplifier S/A, a latch circuit LD, and a buffer
260
. Though only one is illustrated, the select transistors
230
have their gates connected to the column select lines SR
0
to SR
3
and their sources connected to bit lines BL selected by the column selector CS. The bias control transistor
240
has its gate connected to receive the level control signal LVLDWN from the level control circuit LVLGEN and its source connected to a bit line selected by the select transistors
230
(the drains of the transistors
230
). The bit line precharging transistor
250
has its gate connected to receive the precharge signal PRCV from the read control circuit CNTROL
1
, its source connected to a power supply and its drain connected to the drain of the bias control transistor
240
(bit line). The node between the drains of the transistors
240
and
250
is connected to an input terminal VIN of the sense amplifier S/A. The circuit arrangement of the sense amplifier S/A will be described with reference to FIG.
2
B.
As shown, the sense amplifier S/A is a current mirror type of sense amplifier having two pMOS transistors
400
-
1
and
400
-
2
, three nMOS transistors
410
-
1
to
410
-
3
, and an inverter
420
. The sense amplifier is enabled when the control signal PSV input to its enable terminal EN is asserted.
The reference voltage generating circuit REF_VOL applies a reference voltage RF to a reference voltage input terminal VREF of the sense amplifier S/A. The reference voltage generating circuit REF_VOL includes, as shown, three pMOS transistors
270
-
1
to
270
-
3
and one nMOS transistor
280
. The transistor
280
is turned on when the control signal PSV is asserted, i.e., raised to a high level. As a result, a fixed reference voltage RF determined by the transistors
270
-
2
and
270
-
3
is applied to the sense amplifier S/A.
The latch circuit LD is responsive to a data latch clock signal ACT
2
to hold read data VDATA output from the output terminal VOUT of the sense amplifier S/A.
The buffer
260
holds read data LDT from the latch circuit LD and responds to an output control signal CSRD output from the read control circuit CNTROL
1
to output the data onto the data bus DBUS.
The read operation of the flash memory thus configured will be described next with reference to a timing diagram of FIG.
3
A.
First, the CPU in the microcomputer outputs address signals A
18
to A
2
synchronously with the system clock CLK. The address signals identify all locations on the microcomputer including the flash memory. When the address signals are decoded and identify the flash memory
200
, the address select signal ROMCS is asserted (driven to the high level). The read control circuit CNTROL
1
performs a logical NAND operation on the clock CLK and

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