Semiconductor memory device having switching and memory cell...

Details Semiconductor memory device having switching and memory cell... Semiconductor memory device having switching and memory cell...

2000-03-24

2002-10-15

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S063000, C365S189090, C365S230030

Reexamination Certificate

active

06466502

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as a dynamic RAM (Random Access Memory) suitable for integration on a semiconductor substrate together with a logic circuit.
2. Description of the Background Art
Conventionally, logic circuits and dynamic RAMs (DRAM) of microprocessors and application specific integrated circuits (ASIC) have been produced as large scale integrated circuits (VLSI, ULSI, and the like) of high performance in accordance with increase of the integration density. These integrated circuits are produced respectively as individual chips, and connected to an external line on a system board in systems of personal computers.
It has become difficult to improve the high performance of the computer in such systems since the computing ability of the computer is restricted by the parasitic capacitance and resistance of the external wiring. Recently, an approach of improving the high performance has been effected by forming the logic circuit and the DRAM on the same semiconductor substrate.
Particularly, providing the metal wiring of the logic circuit in multilayers has been implemented. Development of multilayer metal wiring such as six or seven layers is in progress.
FIGS. 1A
to
3
B schematically show a fabrication process of a conventional semiconductor memory device having a DRAM formed of two metal interconnection layers and a logic circuit utilizing this DRAM embedded on the same semiconductor substrate.
FIGS. 1A-3A
correspond to the partial sectional views of the DRAM region whereas
FIGS. 1B-3B
correspond to the partial cross sectional views of the logic circuit region.
As shown in
FIGS. 1A and 1B
, following the formation of a field oxide film
2
for element isolation on an Si (silicon) substrate
1
, a gate oxide film
3
, a gate electrode
4
of a transistor of polycrystalline silicon, a word line (gate line)
4
a
, a silicon oxide film
5
thereon, and diffusion layers
6
and
6
a
are formed. An interlayer insulation film
217
is formed thereon by CVD. Then, an opening is formed at a portion of interlayer insulation film
217
for capacitor formation by a photoresist process and dry etching process.
As to the DRAM region, the process of thin film deposition, photoresist and dry etching is repeated to sequentially form a storage electrode
201
of the memory cell capacitor shown in
FIG. 2A
, a capacitor insulating film
202
, and a cell plate electrode
203
. Then, an interlayer insulating film
204
is formed thereon including the logic circuit region.
As to the same DRAM region, the above wiring and interlayer insulating film are deposited alternately and processed to form a bit line
206
constituted by a polycrystalline silicon film and a tungsten polycide film, and a contact hole
205
connecting bit line
206
with diffusion layer
6
a
. Then, an interlayer insulating film
207
is formed thereon including the logic circuit region.
In the above semiconductor memory device having a DRAM region and a logic circuit region embedded, a memory cell is formed of a memory cell transistor for address selection and a memory cell capacitor for data storage. The data storage operation is effected by storing charge in the memory cell capacitor. The amount of stored charge must be increased in order to read out data properly and speedily, and in order to lengthen the data retaining time.
The amount of charge stored in the memory cell capacitor of a DRAM is proportional to the voltage written into the memory cell. The write voltage of H (logical high) data is represented as below.
write voltage={&agr;
Vcc
−(
Vtn
+&bgr;)·&ggr;}  {circle around (1)}
Here,
&agr;: time function depending upon the time constant by the parasitic capacitance and resistance from the power supply voltage source up to the memory cell (&agr;≦1)
&bgr;: increase in threshold value depending upon back bias value
&ggr;: coefficient depending upon write characteristics and operating cycle (&ggr;≦1)
Vcc: power supply voltage
Vtn: threshold of memory cell transistor
In such a DRAM, the write voltage can be increased by minimizing the second term (Vtn+&bgr;) of equation {circle around (1)}. In general, the voltage of the word line is set higher than power supply voltage Vcc to cancel the minus of the second term.
In the case where the DRAM region and the logic circuit region are mounted together, it is desirable to form respective gate oxide films
3
of the logic circuit region and the DRAM region by the same step to simplify the oxide film formation step, as shown in
FIGS. 1A
to
3
B. In this case, the thickness of respective gate oxide films
3
of the logic circuit region and the DRAM region becomes identical. From the standpoint of high speed, gate oxide film
3
of the logic circuit region is set relatively thin, so that gate oxide film
3
of the DRAM region is inevitably also thin. As a result, the voltage on the word line cannot be boosted since it is necessary to ensure the reliability of gate oxide film
3
of the DRAM region. This induces the problem that it is difficult to increase the write voltage, i.e. the amount of stored charge.
As an approach to solve this problem, Japanese Patent Laying-Open No. 10-134570 discloses the usage of a transistor having a threshold value lower than that of the general one (approximately 0.6 V) for the memory cell. Accordingly, the second term of the aforementioned equation {circle around (1)} can be reduced.
In this conventional art, the so-called shared sense amplifier system is employed. The sense amplifier is connected via the switching transistors disposed at both sides to the bit line pair arranged at both sides of the switching transistors. Accordingly, a write voltage is applied to the memory cell capacitor through a switching transistor and a memory cell transistor. In circuitry of such a structure, the voltage applied to the memory cell capacitor depends upon the threshold values of both the switching transistor and the memory cell transistor, and will be reduced by the threshold value of either of the two transistors that has the greater threshold value. When a memory cell transistor that has a low threshold value is employed, the threshold value of the switching transistor must also be of a similar low level.
However, reduction in the threshold value of the switching transistor necessitates the usage of a negative voltage Vbb as the voltage to reliably turn the transistor off. As a result, a circuit that drives in a wide operating range is required, causing the problem of a larger layout area. Furthermore, there is a problem that the load of the Vbb generation circuit becomes heavier to increase the circuit complexity and power consumption.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device that has the write voltage of a memory cell capacitor increased.
According to an aspect of the present invention, a semiconductor memory device includes a first switching transistor for connecting a bit line extending from a memory sub array having a memory cell transistor to a first sense amplifier. The first switching transistor is arranged at a side opposite to the memory sub array than the input side of the sense amplifier.
In the semiconductor memory device of this aspect, the first sense amplifier includes a first P channel sense amplifier and an N channel sense amplifier. The first switching transistor is arranged between the first P channel sense amplifier and N channel sense amplifier to effect isolation and connection therebetween.
According to another aspect of the present invention, a semiconductor memory device includes a first common bit line, a second common bit line, an N channel sense amplifier, a first bit line, a second bit line, a first P channel sense amplifier, a first switching transistor, a second switching transistor, a third bit line, a fourth bit line, a second P channel sense amplifier, a third switching transistor, a fourth switching tran

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