Semiconductor memory device with high-speed sense amplifier

Details Semiconductor memory device with high-speed sense amplifier Semiconductor memory device with high-speed sense amplifier

2005-05-24

2005-05-24

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185130, C365S185200

Reexamination Certificate

active

06898137

ABSTRACT:
In a Vss precharge scheme, dummy cells including a bit line contact, a storage node contact and a third contact connected to a Vccs power supply line are arranged in complementary bit lines. In a waiting state, H level data is written in each dummy cell from the Vccs power supply line. Before row activation is started and a normal word line is selected, a dummy word line is driven to a selected state, and the H level data is read from each dummy cell. Therefore, charge in equal amounts is injected to the complementary bit lines, and a shift from a Vss level to the same potential occurs. A sense amplifier uses the potential as a reference voltage to amplify and detect a potential difference between bit lines.

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Saito, S. et al.; A 1Mb CMOS DRAM with Fast Page and Static Column Modes:,IEEE International Solid-State Circuits Conf. Digest of Tech. Papers, pp. 252-253, (Feb. 15,1985).

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